// SPDX-FileCopyrightText: © 2025 Tenstorrent AI ULC
//
// SPDX-License-Identifier: Apache-2.0

#ifndef OVERLAY_REG_DEFINES_DEBUG_H
#define OVERLAY_REG_DEFINES_DEBUG_H

#include <stdint.h>

//==============================================================================
// Addresses for Address Map: tt_debug_module_apb
//==============================================================================

#define TT_DEBUG_MODULE_APB_REG_MAP_BASE_ADDR (0x0300A000)
#define TT_DEBUG_MODULE_APB_REG_MAP_SIZE (0x00000104)

#define TT_DEBUG_MODULE_APB_DATA_REG_OFFSET (0x00000010)
#define TT_DEBUG_MODULE_APB_DATA_REG_ADDR (0x0300A010)
#define TT_DEBUG_MODULE_APB_DMCONTROL_REG_OFFSET (0x00000040)
#define TT_DEBUG_MODULE_APB_DMCONTROL_REG_ADDR (0x0300A040)
#define TT_DEBUG_MODULE_APB_STATUS_REG_OFFSET (0x00000044)
#define TT_DEBUG_MODULE_APB_STATUS_REG_ADDR (0x0300A044)
#define TT_DEBUG_MODULE_APB_DMI_HARTINFO_REG_OFFSET (0x00000048)
#define TT_DEBUG_MODULE_APB_DMI_HARTINFO_REG_ADDR (0x0300A048)
#define TT_DEBUG_MODULE_APB_HALTSUMMARY1_REG_OFFSET (0x0000004C)
#define TT_DEBUG_MODULE_APB_HALTSUMMARY1_REG_ADDR (0x0300A04C)
#define TT_DEBUG_MODULE_APB_HAWINDOW_REG_OFFSET (0x00000054)
#define TT_DEBUG_MODULE_APB_HAWINDOW_REG_ADDR (0x0300A054)
#define TT_DEBUG_MODULE_APB_ABSTRACTS_REG_OFFSET (0x00000058)
#define TT_DEBUG_MODULE_APB_ABSTRACTS_REG_ADDR (0x0300A058)
#define TT_DEBUG_MODULE_APB_COMMAND_REG_OFFSET (0x0000005C)
#define TT_DEBUG_MODULE_APB_COMMAND_REG_ADDR (0x0300A05C)
#define TT_DEBUG_MODULE_APB_ABSTRACTAUTO_REG_OFFSET (0x00000060)
#define TT_DEBUG_MODULE_APB_ABSTRACTAUTO_REG_ADDR (0x0300A060)
#define TT_DEBUG_MODULE_APB_PROGBUF_REG_OFFSET (0x00000080)
#define TT_DEBUG_MODULE_APB_PROGBUF_REG_ADDR (0x0300A080)
#define TT_DEBUG_MODULE_APB_STATUS2_REG_OFFSET (0x000000C8)
#define TT_DEBUG_MODULE_APB_STATUS2_REG_ADDR (0x0300A0C8)
#define TT_DEBUG_MODULE_APB_SBCS_REG_OFFSET (0x000000E0)
#define TT_DEBUG_MODULE_APB_SBCS_REG_ADDR (0x0300A0E0)
#define TT_DEBUG_MODULE_APB_SBADDR0_REG_OFFSET (0x000000E4)
#define TT_DEBUG_MODULE_APB_SBADDR0_REG_ADDR (0x0300A0E4)
#define TT_DEBUG_MODULE_APB_SBADDR1_REG_OFFSET (0x000000E8)
#define TT_DEBUG_MODULE_APB_SBADDR1_REG_ADDR (0x0300A0E8)
#define TT_DEBUG_MODULE_APB_SBDATA0_REG_OFFSET (0x000000F0)
#define TT_DEBUG_MODULE_APB_SBDATA0_REG_ADDR (0x0300A0F0)
#define TT_DEBUG_MODULE_APB_SBDATA1_REG_OFFSET (0x000000F4)
#define TT_DEBUG_MODULE_APB_SBDATA1_REG_ADDR (0x0300A0F4)
#define TT_DEBUG_MODULE_APB_HALTSUMMARY0_REG_OFFSET (0x00000100)
#define TT_DEBUG_MODULE_APB_HALTSUMMARY0_REG_ADDR (0x0300A100)

//==============================================================================
// Addresses for Address Map: smn
//==============================================================================

#define SMN_REG_MAP_BASE_ADDR (0x03010000)
#define SMN_REG_MAP_SIZE (0x00009050)

//==============================================================================
// Addresses for Address Map: smn_mst_common_block
//==============================================================================

#define SMN_SMN_MST_COMMON_BLOCK_REG_MAP_BASE_ADDR (0x03010000)
#define SMN_SMN_MST_COMMON_BLOCK_REG_MAP_SIZE (0x000000C8)

#define SMN_SMN_MST_COMMON_BLOCK_SMN_MST_CTRL_REG_OFFSET (0x00000000)
#define SMN_SMN_MST_COMMON_BLOCK_SMN_MST_CTRL_REG_ADDR (0x03010000)
#define SMN_SMN_MST_COMMON_BLOCK_SMN_MST_CMD_TIMEOUT_REG_OFFSET (0x00000008)
#define SMN_SMN_MST_COMMON_BLOCK_SMN_MST_CMD_TIMEOUT_REG_ADDR (0x03010008)
#define SMN_SMN_MST_COMMON_BLOCK_SMN_MST_RESP_TIMEOUT_REG_OFFSET (0x00000010)
#define SMN_SMN_MST_COMMON_BLOCK_SMN_MST_RESP_TIMEOUT_REG_ADDR (0x03010010)
#define SMN_SMN_MST_COMMON_BLOCK_SMN_MST_RESP_INT_THD_REG_OFFSET (0x00000018)
#define SMN_SMN_MST_COMMON_BLOCK_SMN_MST_RESP_INT_THD_REG_ADDR (0x03010018)
#define SMN_SMN_MST_COMMON_BLOCK_SMN_MST_STATUS_REG_OFFSET (0x00000020)
#define SMN_SMN_MST_COMMON_BLOCK_SMN_MST_STATUS_REG_ADDR (0x03010020)
#define SMN_SMN_MST_COMMON_BLOCK_SMN_MST_CMD_DESC_QUEUE_STATUS_REG_OFFSET (0x00000028)
#define SMN_SMN_MST_COMMON_BLOCK_SMN_MST_CMD_DESC_QUEUE_STATUS_REG_ADDR (0x03010028)
#define SMN_SMN_MST_COMMON_BLOCK_SMN_MST_CMD_DATA_QUEUE_STATUS_REG_OFFSET (0x00000030)
#define SMN_SMN_MST_COMMON_BLOCK_SMN_MST_CMD_DATA_QUEUE_STATUS_REG_ADDR (0x03010030)
#define SMN_SMN_MST_COMMON_BLOCK_SMN_MST_RESP_DESC_QUEUE_STATUS_REG_OFFSET (0x00000038)
#define SMN_SMN_MST_COMMON_BLOCK_SMN_MST_RESP_DESC_QUEUE_STATUS_REG_ADDR (0x03010038)
#define SMN_SMN_MST_COMMON_BLOCK_SMN_MST_RESP_DATA_QUEUE_STATUS_REG_OFFSET (0x00000040)
#define SMN_SMN_MST_COMMON_BLOCK_SMN_MST_RESP_DATA_QUEUE_STATUS_REG_ADDR (0x03010040)
#define SMN_SMN_MST_COMMON_BLOCK_SMN_MST_OUTST_DESC_QUEUE_STATUS_REG_OFFSET (0x00000048)
#define SMN_SMN_MST_COMMON_BLOCK_SMN_MST_OUTST_DESC_QUEUE_STATUS_REG_ADDR (0x03010048)
#define SMN_SMN_MST_COMMON_BLOCK_SMN_MST_ERROR_STATUS_REG_OFFSET (0x00000050)
#define SMN_SMN_MST_COMMON_BLOCK_SMN_MST_ERROR_STATUS_REG_ADDR (0x03010050)
#define SMN_SMN_MST_COMMON_BLOCK_SMN_MST_EXP_DESC_HDR_REG_OFFSET (0x00000058)
#define SMN_SMN_MST_COMMON_BLOCK_SMN_MST_EXP_DESC_HDR_REG_ADDR (0x03010058)
#define SMN_SMN_MST_COMMON_BLOCK_SMN_MST_EXP_DESC_CMD_REG_OFFSET (0x00000060)
#define SMN_SMN_MST_COMMON_BLOCK_SMN_MST_EXP_DESC_CMD_REG_ADDR (0x03010060)
#define SMN_SMN_MST_COMMON_BLOCK_SMN_MST_EXP_DESC_ADDR_REG_OFFSET (0x00000068)
#define SMN_SMN_MST_COMMON_BLOCK_SMN_MST_EXP_DESC_ADDR_REG_ADDR (0x03010068)
#define SMN_SMN_MST_COMMON_BLOCK_SMN_MST_EXP_DESC_EOF_REG_OFFSET (0x00000070)
#define SMN_SMN_MST_COMMON_BLOCK_SMN_MST_EXP_DESC_EOF_REG_ADDR (0x03010070)
#define SMN_SMN_MST_COMMON_BLOCK_SMN_MST_RECVD_DESC_HDR_REG_OFFSET (0x00000078)
#define SMN_SMN_MST_COMMON_BLOCK_SMN_MST_RECVD_DESC_HDR_REG_ADDR (0x03010078)
#define SMN_SMN_MST_COMMON_BLOCK_SMN_MST_RECVD_DESC_CMD_REG_OFFSET (0x00000080)
#define SMN_SMN_MST_COMMON_BLOCK_SMN_MST_RECVD_DESC_CMD_REG_ADDR (0x03010080)
#define SMN_SMN_MST_COMMON_BLOCK_SMN_MST_RECVD_DESC_ADDR_REG_OFFSET (0x00000088)
#define SMN_SMN_MST_COMMON_BLOCK_SMN_MST_RECVD_DESC_ADDR_REG_ADDR (0x03010088)
#define SMN_SMN_MST_COMMON_BLOCK_SMN_MST_RECVD_DESC_EOF_REG_OFFSET (0x00000090)
#define SMN_SMN_MST_COMMON_BLOCK_SMN_MST_RECVD_DESC_EOF_REG_ADDR (0x03010090)
#define SMN_SMN_MST_COMMON_BLOCK_SMN_MST_INT_ENABLE_REG_OFFSET (0x00000098)
#define SMN_SMN_MST_COMMON_BLOCK_SMN_MST_INT_ENABLE_REG_ADDR (0x03010098)
#define SMN_SMN_MST_COMMON_BLOCK_SMN_MST_INT_STATUS_REG_OFFSET (0x000000A0)
#define SMN_SMN_MST_COMMON_BLOCK_SMN_MST_INT_STATUS_REG_ADDR (0x030100A0)
#define SMN_SMN_MST_COMMON_BLOCK_SMN_MST_INT_STATUS_RAW_REG_OFFSET (0x000000A8)
#define SMN_SMN_MST_COMMON_BLOCK_SMN_MST_INT_STATUS_RAW_REG_ADDR (0x030100A8)
#define SMN_SMN_MST_COMMON_BLOCK_SMN_MST_INT_CLEAR_REG_OFFSET (0x000000B0)
#define SMN_SMN_MST_COMMON_BLOCK_SMN_MST_INT_CLEAR_REG_ADDR (0x030100B0)
#define SMN_SMN_MST_COMMON_BLOCK_SMN_FRAME_CNT_REG_OFFSET (0x000000B8)
#define SMN_SMN_MST_COMMON_BLOCK_SMN_FRAME_CNT_REG_ADDR (0x030100B8)
#define SMN_SMN_MST_COMMON_BLOCK_SMN_FRAME_ERR_CNT_REG_OFFSET (0x000000C0)
#define SMN_SMN_MST_COMMON_BLOCK_SMN_FRAME_ERR_CNT_REG_ADDR (0x030100C0)

//==============================================================================
// Addresses for Address Map: smn_mst_main_block
//==============================================================================

#define SMN_SMN_MST_MAIN_BLOCK_REG_MAP_BASE_ADDR (0x03011000)
#define SMN_SMN_MST_MAIN_BLOCK_REG_MAP_SIZE (0x00000058)

#define SMN_SMN_MST_MAIN_BLOCK_SMN_MST_TOKEN_CONFIG_REG_OFFSET (0x00000000)
#define SMN_SMN_MST_MAIN_BLOCK_SMN_MST_TOKEN_CONFIG_REG_ADDR (0x03011000)
#define SMN_SMN_MST_MAIN_BLOCK_SMN_MST_TOKEN_TIMER_REG_OFFSET (0x00000008)
#define SMN_SMN_MST_MAIN_BLOCK_SMN_MST_TOKEN_TIMER_REG_ADDR (0x03011008)
#define SMN_SMN_MST_MAIN_BLOCK_SMN_MST_IDLE_TOKEN_TIMER_REG_OFFSET (0x00000010)
#define SMN_SMN_MST_MAIN_BLOCK_SMN_MST_IDLE_TOKEN_TIMER_REG_ADDR (0x03011010)
#define SMN_SMN_MST_MAIN_BLOCK_SMN_MST_TOKEN_COUNTER_REG_OFFSET (0x00000018)
#define SMN_SMN_MST_MAIN_BLOCK_SMN_MST_TOKEN_COUNTER_REG_ADDR (0x03011018)
#define SMN_SMN_MST_MAIN_BLOCK_SMN_MST_TOKEN_RETURN_TIMEOUT_REG_OFFSET (0x00000020)
#define SMN_SMN_MST_MAIN_BLOCK_SMN_MST_TOKEN_RETURN_TIMEOUT_REG_ADDR (0x03011020)
#define SMN_SMN_MST_MAIN_BLOCK_SMN_MST_TOKEN_SENT_CNT_REG_OFFSET (0x00000028)
#define SMN_SMN_MST_MAIN_BLOCK_SMN_MST_TOKEN_SENT_CNT_REG_ADDR (0x03011028)
#define SMN_SMN_MST_MAIN_BLOCK_SMN_MST_TOKEN_USED_CNT_REG_OFFSET (0x00000030)
#define SMN_SMN_MST_MAIN_BLOCK_SMN_MST_TOKEN_USED_CNT_REG_ADDR (0x03011030)
#define SMN_SMN_MST_MAIN_BLOCK_SMN_MST_TOKEN_REQ_CNT_REG_OFFSET (0x00000038)
#define SMN_SMN_MST_MAIN_BLOCK_SMN_MST_TOKEN_REQ_CNT_REG_ADDR (0x03011038)
#define SMN_SMN_MST_MAIN_BLOCK_SMN_MST_TOKEN_STATUS_REG_OFFSET (0x00000040)
#define SMN_SMN_MST_MAIN_BLOCK_SMN_MST_TOKEN_STATUS_REG_ADDR (0x03011040)
#define SMN_SMN_MST_MAIN_BLOCK_SMN_MST_TOKEN_FRAME_CNT_REG_OFFSET (0x00000048)
#define SMN_SMN_MST_MAIN_BLOCK_SMN_MST_TOKEN_FRAME_CNT_REG_ADDR (0x03011048)
#define SMN_SMN_MST_MAIN_BLOCK_SMN_MST_NETWORK_ERR_REG_OFFSET (0x00000050)
#define SMN_SMN_MST_MAIN_BLOCK_SMN_MST_NETWORK_ERR_REG_ADDR (0x03011050)

//==============================================================================
// Addresses for Address Map: smn_addr_trans_block
//==============================================================================

#define SMN_SMN_ADDR_TRANS_BLOCK_REG_MAP_BASE_ADDR (0x03012000)
#define SMN_SMN_ADDR_TRANS_BLOCK_REG_MAP_SIZE (0x00000488)

#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_MASK_TABLE_CFG_0__REG_OFFSET (0x00000000)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_MASK_TABLE_CFG_0__REG_ADDR (0x03012000)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_MASK_TABLE_CFG_1__REG_OFFSET (0x00000008)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_MASK_TABLE_CFG_1__REG_ADDR (0x03012008)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_MASK_TABLE_CFG_2__REG_OFFSET (0x00000010)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_MASK_TABLE_CFG_2__REG_ADDR (0x03012010)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_MASK_TABLE_CFG_3__REG_OFFSET (0x00000018)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_MASK_TABLE_CFG_3__REG_ADDR (0x03012018)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_MASK_TABLE_CFG_4__REG_OFFSET (0x00000020)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_MASK_TABLE_CFG_4__REG_ADDR (0x03012020)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_MASK_TABLE_CFG_5__REG_OFFSET (0x00000028)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_MASK_TABLE_CFG_5__REG_ADDR (0x03012028)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_MASK_TABLE_CFG_6__REG_OFFSET (0x00000030)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_MASK_TABLE_CFG_6__REG_ADDR (0x03012030)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_MASK_TABLE_CFG_7__REG_OFFSET (0x00000038)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_MASK_TABLE_CFG_7__REG_ADDR (0x03012038)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_MASK_TABLE_CFG_8__REG_OFFSET (0x00000040)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_MASK_TABLE_CFG_8__REG_ADDR (0x03012040)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_MASK_TABLE_CFG_9__REG_OFFSET (0x00000048)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_MASK_TABLE_CFG_9__REG_ADDR (0x03012048)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_MASK_TABLE_CFG_10__REG_OFFSET (0x00000050)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_MASK_TABLE_CFG_10__REG_ADDR (0x03012050)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_MASK_TABLE_CFG_11__REG_OFFSET (0x00000058)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_MASK_TABLE_CFG_11__REG_ADDR (0x03012058)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_MASK_TABLE_CFG_12__REG_OFFSET (0x00000060)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_MASK_TABLE_CFG_12__REG_ADDR (0x03012060)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_MASK_TABLE_CFG_13__REG_OFFSET (0x00000068)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_MASK_TABLE_CFG_13__REG_ADDR (0x03012068)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_MASK_TABLE_CFG_14__REG_OFFSET (0x00000070)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_MASK_TABLE_CFG_14__REG_ADDR (0x03012070)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_MASK_TABLE_CFG_15__REG_OFFSET (0x00000078)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_MASK_TABLE_CFG_15__REG_ADDR (0x03012078)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_0__REG_OFFSET (0x00000080)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_0__REG_ADDR (0x03012080)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_1__REG_OFFSET (0x00000088)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_1__REG_ADDR (0x03012088)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_2__REG_OFFSET (0x00000090)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_2__REG_ADDR (0x03012090)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_3__REG_OFFSET (0x00000098)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_3__REG_ADDR (0x03012098)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_4__REG_OFFSET (0x000000A0)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_4__REG_ADDR (0x030120A0)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_5__REG_OFFSET (0x000000A8)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_5__REG_ADDR (0x030120A8)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_6__REG_OFFSET (0x000000B0)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_6__REG_ADDR (0x030120B0)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_7__REG_OFFSET (0x000000B8)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_7__REG_ADDR (0x030120B8)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_8__REG_OFFSET (0x000000C0)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_8__REG_ADDR (0x030120C0)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_9__REG_OFFSET (0x000000C8)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_9__REG_ADDR (0x030120C8)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_10__REG_OFFSET (0x000000D0)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_10__REG_ADDR (0x030120D0)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_11__REG_OFFSET (0x000000D8)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_11__REG_ADDR (0x030120D8)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_12__REG_OFFSET (0x000000E0)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_12__REG_ADDR (0x030120E0)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_13__REG_OFFSET (0x000000E8)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_13__REG_ADDR (0x030120E8)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_14__REG_OFFSET (0x000000F0)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_14__REG_ADDR (0x030120F0)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_15__REG_OFFSET (0x000000F8)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_15__REG_ADDR (0x030120F8)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_16__REG_OFFSET (0x00000100)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_16__REG_ADDR (0x03012100)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_17__REG_OFFSET (0x00000108)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_17__REG_ADDR (0x03012108)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_18__REG_OFFSET (0x00000110)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_18__REG_ADDR (0x03012110)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_19__REG_OFFSET (0x00000118)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_19__REG_ADDR (0x03012118)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_20__REG_OFFSET (0x00000120)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_20__REG_ADDR (0x03012120)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_21__REG_OFFSET (0x00000128)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_21__REG_ADDR (0x03012128)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_22__REG_OFFSET (0x00000130)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_22__REG_ADDR (0x03012130)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_23__REG_OFFSET (0x00000138)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_23__REG_ADDR (0x03012138)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_24__REG_OFFSET (0x00000140)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_24__REG_ADDR (0x03012140)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_25__REG_OFFSET (0x00000148)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_25__REG_ADDR (0x03012148)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_26__REG_OFFSET (0x00000150)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_26__REG_ADDR (0x03012150)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_27__REG_OFFSET (0x00000158)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_27__REG_ADDR (0x03012158)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_28__REG_OFFSET (0x00000160)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_28__REG_ADDR (0x03012160)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_29__REG_OFFSET (0x00000168)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_29__REG_ADDR (0x03012168)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_30__REG_OFFSET (0x00000170)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_30__REG_ADDR (0x03012170)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_31__REG_OFFSET (0x00000178)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_31__REG_ADDR (0x03012178)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_32__REG_OFFSET (0x00000180)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_32__REG_ADDR (0x03012180)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_33__REG_OFFSET (0x00000188)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_33__REG_ADDR (0x03012188)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_34__REG_OFFSET (0x00000190)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_34__REG_ADDR (0x03012190)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_35__REG_OFFSET (0x00000198)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_35__REG_ADDR (0x03012198)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_36__REG_OFFSET (0x000001A0)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_36__REG_ADDR (0x030121A0)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_37__REG_OFFSET (0x000001A8)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_37__REG_ADDR (0x030121A8)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_38__REG_OFFSET (0x000001B0)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_38__REG_ADDR (0x030121B0)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_39__REG_OFFSET (0x000001B8)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_39__REG_ADDR (0x030121B8)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_40__REG_OFFSET (0x000001C0)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_40__REG_ADDR (0x030121C0)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_41__REG_OFFSET (0x000001C8)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_41__REG_ADDR (0x030121C8)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_42__REG_OFFSET (0x000001D0)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_42__REG_ADDR (0x030121D0)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_43__REG_OFFSET (0x000001D8)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_43__REG_ADDR (0x030121D8)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_44__REG_OFFSET (0x000001E0)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_44__REG_ADDR (0x030121E0)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_45__REG_OFFSET (0x000001E8)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_45__REG_ADDR (0x030121E8)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_46__REG_OFFSET (0x000001F0)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_46__REG_ADDR (0x030121F0)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_47__REG_OFFSET (0x000001F8)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_47__REG_ADDR (0x030121F8)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_48__REG_OFFSET (0x00000200)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_48__REG_ADDR (0x03012200)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_49__REG_OFFSET (0x00000208)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_49__REG_ADDR (0x03012208)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_50__REG_OFFSET (0x00000210)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_50__REG_ADDR (0x03012210)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_51__REG_OFFSET (0x00000218)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_51__REG_ADDR (0x03012218)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_52__REG_OFFSET (0x00000220)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_52__REG_ADDR (0x03012220)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_53__REG_OFFSET (0x00000228)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_53__REG_ADDR (0x03012228)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_54__REG_OFFSET (0x00000230)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_54__REG_ADDR (0x03012230)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_55__REG_OFFSET (0x00000238)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_55__REG_ADDR (0x03012238)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_56__REG_OFFSET (0x00000240)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_56__REG_ADDR (0x03012240)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_57__REG_OFFSET (0x00000248)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_57__REG_ADDR (0x03012248)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_58__REG_OFFSET (0x00000250)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_58__REG_ADDR (0x03012250)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_59__REG_OFFSET (0x00000258)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_59__REG_ADDR (0x03012258)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_60__REG_OFFSET (0x00000260)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_60__REG_ADDR (0x03012260)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_61__REG_OFFSET (0x00000268)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_61__REG_ADDR (0x03012268)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_62__REG_OFFSET (0x00000270)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_62__REG_ADDR (0x03012270)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_63__REG_OFFSET (0x00000278)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_63__REG_ADDR (0x03012278)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_64__REG_OFFSET (0x00000280)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_64__REG_ADDR (0x03012280)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_65__REG_OFFSET (0x00000288)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_65__REG_ADDR (0x03012288)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_66__REG_OFFSET (0x00000290)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_66__REG_ADDR (0x03012290)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_67__REG_OFFSET (0x00000298)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_67__REG_ADDR (0x03012298)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_68__REG_OFFSET (0x000002A0)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_68__REG_ADDR (0x030122A0)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_69__REG_OFFSET (0x000002A8)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_69__REG_ADDR (0x030122A8)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_70__REG_OFFSET (0x000002B0)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_70__REG_ADDR (0x030122B0)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_71__REG_OFFSET (0x000002B8)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_71__REG_ADDR (0x030122B8)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_72__REG_OFFSET (0x000002C0)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_72__REG_ADDR (0x030122C0)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_73__REG_OFFSET (0x000002C8)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_73__REG_ADDR (0x030122C8)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_74__REG_OFFSET (0x000002D0)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_74__REG_ADDR (0x030122D0)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_75__REG_OFFSET (0x000002D8)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_75__REG_ADDR (0x030122D8)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_76__REG_OFFSET (0x000002E0)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_76__REG_ADDR (0x030122E0)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_77__REG_OFFSET (0x000002E8)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_77__REG_ADDR (0x030122E8)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_78__REG_OFFSET (0x000002F0)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_78__REG_ADDR (0x030122F0)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_79__REG_OFFSET (0x000002F8)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_79__REG_ADDR (0x030122F8)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_80__REG_OFFSET (0x00000300)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_80__REG_ADDR (0x03012300)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_81__REG_OFFSET (0x00000308)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_81__REG_ADDR (0x03012308)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_82__REG_OFFSET (0x00000310)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_82__REG_ADDR (0x03012310)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_83__REG_OFFSET (0x00000318)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_83__REG_ADDR (0x03012318)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_84__REG_OFFSET (0x00000320)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_84__REG_ADDR (0x03012320)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_85__REG_OFFSET (0x00000328)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_85__REG_ADDR (0x03012328)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_86__REG_OFFSET (0x00000330)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_86__REG_ADDR (0x03012330)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_87__REG_OFFSET (0x00000338)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_87__REG_ADDR (0x03012338)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_88__REG_OFFSET (0x00000340)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_88__REG_ADDR (0x03012340)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_89__REG_OFFSET (0x00000348)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_89__REG_ADDR (0x03012348)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_90__REG_OFFSET (0x00000350)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_90__REG_ADDR (0x03012350)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_91__REG_OFFSET (0x00000358)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_91__REG_ADDR (0x03012358)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_92__REG_OFFSET (0x00000360)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_92__REG_ADDR (0x03012360)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_93__REG_OFFSET (0x00000368)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_93__REG_ADDR (0x03012368)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_94__REG_OFFSET (0x00000370)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_94__REG_ADDR (0x03012370)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_95__REG_OFFSET (0x00000378)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_95__REG_ADDR (0x03012378)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_96__REG_OFFSET (0x00000380)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_96__REG_ADDR (0x03012380)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_97__REG_OFFSET (0x00000388)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_97__REG_ADDR (0x03012388)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_98__REG_OFFSET (0x00000390)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_98__REG_ADDR (0x03012390)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_99__REG_OFFSET (0x00000398)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_99__REG_ADDR (0x03012398)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_100__REG_OFFSET (0x000003A0)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_100__REG_ADDR (0x030123A0)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_101__REG_OFFSET (0x000003A8)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_101__REG_ADDR (0x030123A8)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_102__REG_OFFSET (0x000003B0)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_102__REG_ADDR (0x030123B0)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_103__REG_OFFSET (0x000003B8)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_103__REG_ADDR (0x030123B8)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_104__REG_OFFSET (0x000003C0)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_104__REG_ADDR (0x030123C0)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_105__REG_OFFSET (0x000003C8)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_105__REG_ADDR (0x030123C8)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_106__REG_OFFSET (0x000003D0)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_106__REG_ADDR (0x030123D0)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_107__REG_OFFSET (0x000003D8)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_107__REG_ADDR (0x030123D8)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_108__REG_OFFSET (0x000003E0)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_108__REG_ADDR (0x030123E0)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_109__REG_OFFSET (0x000003E8)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_109__REG_ADDR (0x030123E8)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_110__REG_OFFSET (0x000003F0)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_110__REG_ADDR (0x030123F0)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_111__REG_OFFSET (0x000003F8)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_111__REG_ADDR (0x030123F8)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_112__REG_OFFSET (0x00000400)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_112__REG_ADDR (0x03012400)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_113__REG_OFFSET (0x00000408)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_113__REG_ADDR (0x03012408)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_114__REG_OFFSET (0x00000410)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_114__REG_ADDR (0x03012410)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_115__REG_OFFSET (0x00000418)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_115__REG_ADDR (0x03012418)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_116__REG_OFFSET (0x00000420)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_116__REG_ADDR (0x03012420)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_117__REG_OFFSET (0x00000428)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_117__REG_ADDR (0x03012428)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_118__REG_OFFSET (0x00000430)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_118__REG_ADDR (0x03012430)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_119__REG_OFFSET (0x00000438)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_119__REG_ADDR (0x03012438)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_120__REG_OFFSET (0x00000440)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_120__REG_ADDR (0x03012440)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_121__REG_OFFSET (0x00000448)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_121__REG_ADDR (0x03012448)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_122__REG_OFFSET (0x00000450)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_122__REG_ADDR (0x03012450)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_123__REG_OFFSET (0x00000458)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_123__REG_ADDR (0x03012458)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_124__REG_OFFSET (0x00000460)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_124__REG_ADDR (0x03012460)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_125__REG_OFFSET (0x00000468)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_125__REG_ADDR (0x03012468)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_126__REG_OFFSET (0x00000470)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_126__REG_ADDR (0x03012470)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_127__REG_OFFSET (0x00000478)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_EP_TABLE_CFG_127__REG_ADDR (0x03012478)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_ERR_STS_REG_OFFSET (0x00000480)
#define SMN_SMN_ADDR_TRANS_BLOCK_SMN_ADDR_TRANS_ERR_STS_REG_ADDR (0x03012480)

//==============================================================================
// Addresses for Address Map: smn_mst_cmd_buf
//==============================================================================

#define SMN_SMN_MST_CMD_BUF_REG_MAP_BASE_ADDR (0x03013000)
#define SMN_SMN_MST_CMD_BUF_REG_MAP_SIZE (0x00000010)

#define SMN_SMN_MST_CMD_BUF_SMN_MST_CMD_BUF_REG0_REG_OFFSET (0x00000000)
#define SMN_SMN_MST_CMD_BUF_SMN_MST_CMD_BUF_REG0_REG_ADDR (0x03013000)
#define SMN_SMN_MST_CMD_BUF_SMN_MST_CMD_BUF_REG1_REG_OFFSET (0x00000008)
#define SMN_SMN_MST_CMD_BUF_SMN_MST_CMD_BUF_REG1_REG_ADDR (0x03013008)

//==============================================================================
// Memory: smn_mst_cmd_data_queue
//==============================================================================

#define SMN_SMN_MST_CMD_DATA_QUEUE_MEM_BASE_ADDR (0x03014000)
#define SMN_SMN_MST_CMD_DATA_QUEUE_MEM_SIZE (0x00001000)

//==============================================================================
// Memory: smn_mst_resp_desc_queue
//==============================================================================

#define SMN_SMN_MST_RESP_DESC_QUEUE_MEM_BASE_ADDR (0x03015000)
#define SMN_SMN_MST_RESP_DESC_QUEUE_MEM_SIZE (0x00000020)

//==============================================================================
// Memory: smn_mst_resp_desc_queue_32b
//==============================================================================

#define SMN_SMN_MST_RESP_DESC_QUEUE_32B_MEM_BASE_ADDR (0x03015020)
#define SMN_SMN_MST_RESP_DESC_QUEUE_32B_MEM_SIZE (0x00000020)

//==============================================================================
// Memory: smn_mst_resp_data_queue
//==============================================================================

#define SMN_SMN_MST_RESP_DATA_QUEUE_MEM_BASE_ADDR (0x03016000)
#define SMN_SMN_MST_RESP_DATA_QUEUE_MEM_SIZE (0x00000008)

//==============================================================================
// Memory: smn_mst_resp_data_queue_32b
//==============================================================================

#define SMN_SMN_MST_RESP_DATA_QUEUE_32B_MEM_BASE_ADDR (0x03016008)
#define SMN_SMN_MST_RESP_DATA_QUEUE_32B_MEM_SIZE (0x00000008)

//==============================================================================
// Addresses for Address Map: smn_slave_mailbox_0
//==============================================================================

#define SMN_SMN_SLAVE_MAILBOX_0_REG_MAP_BASE_ADDR (0x03017000)
#define SMN_SMN_SLAVE_MAILBOX_0_REG_MAP_SIZE (0x00000050)

#define SMN_SMN_SLAVE_MAILBOX_0_SMN_MBOXW_REG_OFFSET (0x00000000)
#define SMN_SMN_SLAVE_MAILBOX_0_SMN_MBOXW_REG_ADDR (0x03017000)
#define SMN_SMN_SLAVE_MAILBOX_0_SMN_MBOXR_REG_OFFSET (0x00000008)
#define SMN_SMN_SLAVE_MAILBOX_0_SMN_MBOXR_REG_ADDR (0x03017008)
#define SMN_SMN_SLAVE_MAILBOX_0_SMN_MBOX_STATUS_REG_OFFSET (0x00000010)
#define SMN_SMN_SLAVE_MAILBOX_0_SMN_MBOX_STATUS_REG_ADDR (0x03017010)
#define SMN_SMN_SLAVE_MAILBOX_0_SMN_MBOX_ERROR_REG_OFFSET (0x00000018)
#define SMN_SMN_SLAVE_MAILBOX_0_SMN_MBOX_ERROR_REG_ADDR (0x03017018)
#define SMN_SMN_SLAVE_MAILBOX_0_SMN_MBOX_WIRQT_REG_OFFSET (0x00000020)
#define SMN_SMN_SLAVE_MAILBOX_0_SMN_MBOX_WIRQT_REG_ADDR (0x03017020)
#define SMN_SMN_SLAVE_MAILBOX_0_SMN_MBOX_RIRQT_REG_OFFSET (0x00000028)
#define SMN_SMN_SLAVE_MAILBOX_0_SMN_MBOX_RIRQT_REG_ADDR (0x03017028)
#define SMN_SMN_SLAVE_MAILBOX_0_SMN_MBOX_IRQS_REG_OFFSET (0x00000030)
#define SMN_SMN_SLAVE_MAILBOX_0_SMN_MBOX_IRQS_REG_ADDR (0x03017030)
#define SMN_SMN_SLAVE_MAILBOX_0_SMN_MBOX_IRQEN_REG_OFFSET (0x00000038)
#define SMN_SMN_SLAVE_MAILBOX_0_SMN_MBOX_IRQEN_REG_ADDR (0x03017038)
#define SMN_SMN_SLAVE_MAILBOX_0_SMN_MBOX_IRQP_REG_OFFSET (0x00000040)
#define SMN_SMN_SLAVE_MAILBOX_0_SMN_MBOX_IRQP_REG_ADDR (0x03017040)
#define SMN_SMN_SLAVE_MAILBOX_0_SMN_MBOX_CTRL_REG_OFFSET (0x00000048)
#define SMN_SMN_SLAVE_MAILBOX_0_SMN_MBOX_CTRL_REG_ADDR (0x03017048)

//==============================================================================
// Addresses for Address Map: smn_slave_mailbox_1
//==============================================================================

#define SMN_SMN_SLAVE_MAILBOX_1_REG_MAP_BASE_ADDR (0x03017100)
#define SMN_SMN_SLAVE_MAILBOX_1_REG_MAP_SIZE (0x00000050)

#define SMN_SMN_SLAVE_MAILBOX_1_SMN_MBOXW_REG_OFFSET (0x00000000)
#define SMN_SMN_SLAVE_MAILBOX_1_SMN_MBOXW_REG_ADDR (0x03017100)
#define SMN_SMN_SLAVE_MAILBOX_1_SMN_MBOXR_REG_OFFSET (0x00000008)
#define SMN_SMN_SLAVE_MAILBOX_1_SMN_MBOXR_REG_ADDR (0x03017108)
#define SMN_SMN_SLAVE_MAILBOX_1_SMN_MBOX_STATUS_REG_OFFSET (0x00000010)
#define SMN_SMN_SLAVE_MAILBOX_1_SMN_MBOX_STATUS_REG_ADDR (0x03017110)
#define SMN_SMN_SLAVE_MAILBOX_1_SMN_MBOX_ERROR_REG_OFFSET (0x00000018)
#define SMN_SMN_SLAVE_MAILBOX_1_SMN_MBOX_ERROR_REG_ADDR (0x03017118)
#define SMN_SMN_SLAVE_MAILBOX_1_SMN_MBOX_WIRQT_REG_OFFSET (0x00000020)
#define SMN_SMN_SLAVE_MAILBOX_1_SMN_MBOX_WIRQT_REG_ADDR (0x03017120)
#define SMN_SMN_SLAVE_MAILBOX_1_SMN_MBOX_RIRQT_REG_OFFSET (0x00000028)
#define SMN_SMN_SLAVE_MAILBOX_1_SMN_MBOX_RIRQT_REG_ADDR (0x03017128)
#define SMN_SMN_SLAVE_MAILBOX_1_SMN_MBOX_IRQS_REG_OFFSET (0x00000030)
#define SMN_SMN_SLAVE_MAILBOX_1_SMN_MBOX_IRQS_REG_ADDR (0x03017130)
#define SMN_SMN_SLAVE_MAILBOX_1_SMN_MBOX_IRQEN_REG_OFFSET (0x00000038)
#define SMN_SMN_SLAVE_MAILBOX_1_SMN_MBOX_IRQEN_REG_ADDR (0x03017138)
#define SMN_SMN_SLAVE_MAILBOX_1_SMN_MBOX_IRQP_REG_OFFSET (0x00000040)
#define SMN_SMN_SLAVE_MAILBOX_1_SMN_MBOX_IRQP_REG_ADDR (0x03017140)
#define SMN_SMN_SLAVE_MAILBOX_1_SMN_MBOX_CTRL_REG_OFFSET (0x00000048)
#define SMN_SMN_SLAVE_MAILBOX_1_SMN_MBOX_CTRL_REG_ADDR (0x03017148)

//==============================================================================
// Addresses for Address Map: smn_slv_block
//==============================================================================

#define SMN_SMN_SLV_BLOCK_REG_MAP_BASE_ADDR (0x03017800)
#define SMN_SMN_SLV_BLOCK_REG_MAP_SIZE (0x00000238)

#define SMN_SMN_SLV_BLOCK_SMN_SLV_SCRATCH_REG_0__REG_OFFSET (0x00000000)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_SCRATCH_REG_0__REG_ADDR (0x03017800)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_SCRATCH_REG_1__REG_OFFSET (0x00000008)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_SCRATCH_REG_1__REG_ADDR (0x03017808)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_SCRATCH_REG_2__REG_OFFSET (0x00000010)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_SCRATCH_REG_2__REG_ADDR (0x03017810)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_SCRATCH_REG_3__REG_OFFSET (0x00000018)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_SCRATCH_REG_3__REG_ADDR (0x03017818)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_SCRATCH_REG_4__REG_OFFSET (0x00000020)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_SCRATCH_REG_4__REG_ADDR (0x03017820)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_SCRATCH_REG_5__REG_OFFSET (0x00000028)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_SCRATCH_REG_5__REG_ADDR (0x03017828)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_SCRATCH_REG_6__REG_OFFSET (0x00000030)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_SCRATCH_REG_6__REG_ADDR (0x03017830)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_SCRATCH_REG_7__REG_OFFSET (0x00000038)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_SCRATCH_REG_7__REG_ADDR (0x03017838)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_EXT_STATUS_0__REG_OFFSET (0x00000040)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_EXT_STATUS_0__REG_ADDR (0x03017840)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_EXT_STATUS_1__REG_OFFSET (0x00000048)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_EXT_STATUS_1__REG_ADDR (0x03017848)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_EXT_STATUS_2__REG_OFFSET (0x00000050)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_EXT_STATUS_2__REG_ADDR (0x03017850)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_EXT_STATUS_3__REG_OFFSET (0x00000058)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_EXT_STATUS_3__REG_ADDR (0x03017858)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_EXT_STATUS_4__REG_OFFSET (0x00000060)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_EXT_STATUS_4__REG_ADDR (0x03017860)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_EXT_STATUS_5__REG_OFFSET (0x00000068)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_EXT_STATUS_5__REG_ADDR (0x03017868)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_EXT_STATUS_6__REG_OFFSET (0x00000070)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_EXT_STATUS_6__REG_ADDR (0x03017870)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_EXT_STATUS_7__REG_OFFSET (0x00000078)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_EXT_STATUS_7__REG_ADDR (0x03017878)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_EXT_ERROR_REG_OFFSET (0x00000080)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_EXT_ERROR_REG_ADDR (0x03017880)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_INT_CLEAR_REG_OFFSET (0x00000088)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_INT_CLEAR_REG_ADDR (0x03017888)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_INT_ENABLE_REG_OFFSET (0x00000090)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_INT_ENABLE_REG_ADDR (0x03017890)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_INT_STATUS_REG_OFFSET (0x00000098)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_INT_STATUS_REG_ADDR (0x03017898)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_INT_STATUS_RAW_REG_OFFSET (0x000000A0)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_INT_STATUS_RAW_REG_ADDR (0x030178A0)
#define SMN_SMN_SLV_BLOCK_SMN_NODE_CTRL_REG_OFFSET (0x000000A8)
#define SMN_SMN_SLV_BLOCK_SMN_NODE_CTRL_REG_ADDR (0x030178A8)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_CLK_CTRL_REG_OFFSET (0x000000B0)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_CLK_CTRL_REG_ADDR (0x030178B0)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_DEBUG_REG_OFFSET (0x000000B8)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_DEBUG_REG_ADDR (0x030178B8)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_ECC_ERR_CNT_REG_OFFSET (0x000000C0)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_ECC_ERR_CNT_REG_ADDR (0x030178C0)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_PARSER_TIMEOUT_REG_OFFSET (0x000000C8)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_PARSER_TIMEOUT_REG_ADDR (0x030178C8)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_AXI_TIMEOUT_REG_OFFSET (0x000000D0)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_AXI_TIMEOUT_REG_ADDR (0x030178D0)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_ROUTER_TIMEOUT_REG_OFFSET (0x000000D8)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_ROUTER_TIMEOUT_REG_ADDR (0x030178D8)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_FIREWALL_SMN2AXI_0_RANGE_RW_REG_OFFSET (0x000000E0)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_FIREWALL_SMN2AXI_0_RANGE_RW_REG_ADDR (0x030178E0)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_FIREWALL_SMN2AXI_0_START_ADDR_REG_OFFSET (0x000000E8)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_FIREWALL_SMN2AXI_0_START_ADDR_REG_ADDR (0x030178E8)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_FIREWALL_SMN2AXI_0_END_ADDR_REG_OFFSET (0x000000F0)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_FIREWALL_SMN2AXI_0_END_ADDR_REG_ADDR (0x030178F0)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_FIREWALL_SMN2AXI_1_RANGE_RW_REG_OFFSET (0x000000F8)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_FIREWALL_SMN2AXI_1_RANGE_RW_REG_ADDR (0x030178F8)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_FIREWALL_SMN2AXI_1_START_ADDR_REG_OFFSET (0x00000100)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_FIREWALL_SMN2AXI_1_START_ADDR_REG_ADDR (0x03017900)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_FIREWALL_SMN2AXI_1_END_ADDR_REG_OFFSET (0x00000108)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_FIREWALL_SMN2AXI_1_END_ADDR_REG_ADDR (0x03017908)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_FIREWALL_SMN2AXI_2_RANGE_RW_REG_OFFSET (0x00000110)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_FIREWALL_SMN2AXI_2_RANGE_RW_REG_ADDR (0x03017910)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_FIREWALL_SMN2AXI_2_START_ADDR_REG_OFFSET (0x00000118)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_FIREWALL_SMN2AXI_2_START_ADDR_REG_ADDR (0x03017918)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_FIREWALL_SMN2AXI_2_END_ADDR_REG_OFFSET (0x00000120)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_FIREWALL_SMN2AXI_2_END_ADDR_REG_ADDR (0x03017920)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_FIREWALL_SMN2AXI_3_RANGE_RW_REG_OFFSET (0x00000128)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_FIREWALL_SMN2AXI_3_RANGE_RW_REG_ADDR (0x03017928)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_FIREWALL_SMN2AXI_3_START_ADDR_REG_OFFSET (0x00000130)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_FIREWALL_SMN2AXI_3_START_ADDR_REG_ADDR (0x03017930)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_FIREWALL_SMN2AXI_3_END_ADDR_REG_OFFSET (0x00000138)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_FIREWALL_SMN2AXI_3_END_ADDR_REG_ADDR (0x03017938)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_FIREWALL_LOCAL_MST_0_RANGE_RW_REG_OFFSET (0x00000140)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_FIREWALL_LOCAL_MST_0_RANGE_RW_REG_ADDR (0x03017940)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_FIREWALL_LOCAL_MST_0_START_ADDR_REG_OFFSET (0x00000148)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_FIREWALL_LOCAL_MST_0_START_ADDR_REG_ADDR (0x03017948)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_FIREWALL_LOCAL_MST_0_END_ADDR_REG_OFFSET (0x00000150)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_FIREWALL_LOCAL_MST_0_END_ADDR_REG_ADDR (0x03017950)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_FIREWALL_LOCAL_MST_1_RANGE_RW_REG_OFFSET (0x00000158)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_FIREWALL_LOCAL_MST_1_RANGE_RW_REG_ADDR (0x03017958)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_FIREWALL_LOCAL_MST_1_START_ADDR_REG_OFFSET (0x00000160)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_FIREWALL_LOCAL_MST_1_START_ADDR_REG_ADDR (0x03017960)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_FIREWALL_LOCAL_MST_1_END_ADDR_REG_OFFSET (0x00000168)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_FIREWALL_LOCAL_MST_1_END_ADDR_REG_ADDR (0x03017968)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_FIREWALL_LOCAL_MST_2_RANGE_RW_REG_OFFSET (0x00000170)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_FIREWALL_LOCAL_MST_2_RANGE_RW_REG_ADDR (0x03017970)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_FIREWALL_LOCAL_MST_2_START_ADDR_REG_OFFSET (0x00000178)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_FIREWALL_LOCAL_MST_2_START_ADDR_REG_ADDR (0x03017978)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_FIREWALL_LOCAL_MST_2_END_ADDR_REG_OFFSET (0x00000180)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_FIREWALL_LOCAL_MST_2_END_ADDR_REG_ADDR (0x03017980)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_FIREWALL_LOCAL_MST_3_RANGE_RW_REG_OFFSET (0x00000188)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_FIREWALL_LOCAL_MST_3_RANGE_RW_REG_ADDR (0x03017988)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_FIREWALL_LOCAL_MST_3_START_ADDR_REG_OFFSET (0x00000190)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_FIREWALL_LOCAL_MST_3_START_ADDR_REG_ADDR (0x03017990)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_FIREWALL_LOCAL_MST_3_END_ADDR_REG_OFFSET (0x00000198)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_FIREWALL_LOCAL_MST_3_END_ADDR_REG_ADDR (0x03017998)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_AXI_MST_ISOLATE_REG_OFFSET (0x000001A0)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_AXI_MST_ISOLATE_REG_ADDR (0x030179A0)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_ROUTER_ERR_INJ_REG_OFFSET (0x000001A8)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_ROUTER_ERR_INJ_REG_ADDR (0x030179A8)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_TILE_RESET_REG_OFFSET (0x000001B0)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_TILE_RESET_REG_ADDR (0x030179B0)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_TILE_CLKEN_FORCEREF_REG_OFFSET (0x000001B8)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_TILE_CLKEN_FORCEREF_REG_ADDR (0x030179B8)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_TILE_FREQ_SEL_REG_OFFSET (0x000001C0)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_TILE_FREQ_SEL_REG_ADDR (0x030179C0)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_TILE_CLK_WAVE_CTRL_REG_OFFSET (0x000001C8)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_TILE_CLK_WAVE_CTRL_REG_ADDR (0x030179C8)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_TILE_CLK_STATUS_REG_OFFSET (0x000001D0)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_TILE_CLK_STATUS_REG_ADDR (0x030179D0)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_TILE_HARVEST_PD_REG_OFFSET (0x000001D8)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_TILE_HARVEST_PD_REG_ADDR (0x030179D8)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_TILE_MEM_CFG_RA1_UHD_REG_OFFSET (0x000001E0)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_TILE_MEM_CFG_RA1_UHD_REG_ADDR (0x030179E0)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_TILE_MEM_CFG_RF1_UHD_REG_OFFSET (0x000001E8)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_TILE_MEM_CFG_RF1_UHD_REG_ADDR (0x030179E8)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_TILE_MEM_CFG_RA1_HS_REG_OFFSET (0x000001F0)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_TILE_MEM_CFG_RA1_HS_REG_ADDR (0x030179F0)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_TILE_MEM_CFG_RF1_HS_REG_OFFSET (0x000001F8)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_TILE_MEM_CFG_RF1_HS_REG_ADDR (0x030179F8)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_TILE_MEM_CFG_RD2_HS_REG_OFFSET (0x00000200)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_TILE_MEM_CFG_RD2_HS_REG_ADDR (0x03017A00)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_TILE_MEM_CFG_RD2_UHS_REG_OFFSET (0x00000208)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_TILE_MEM_CFG_RD2_UHS_REG_ADDR (0x03017A08)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_PLL_PERFORMANCE_LOCK_REG_OFFSET (0x00000210)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_PLL_PERFORMANCE_LOCK_REG_ADDR (0x03017A10)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_REFCLK_BUMPPAD_REG_OFFSET (0x00000218)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_REFCLK_BUMPPAD_REG_ADDR (0x03017A18)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_NODE_COORD_OVERRIDE_REG_OFFSET (0x00000220)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_NODE_COORD_OVERRIDE_REG_ADDR (0x03017A20)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_TILE_MEM_CFG_RD2_HS_EMC_REG_OFFSET (0x00000228)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_TILE_MEM_CFG_RD2_HS_EMC_REG_ADDR (0x03017A28)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_TILE_MEM_CFG_RA1_UHD_EMC_REG_OFFSET (0x00000230)
#define SMN_SMN_SLV_BLOCK_SMN_SLV_TILE_MEM_CFG_RA1_UHD_EMC_REG_ADDR (0x03017A30)

//==============================================================================
// Addresses for Address Map: smn_slv_noc_sec_block
//==============================================================================

#define SMN_SMN_SLV_NOC_SEC_BLOCK_REG_MAP_BASE_ADDR (0x03018000)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_REG_MAP_SIZE (0x00000138)

#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_X_Y_REG_OFFSET (0x00000000)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_X_Y_REG_ADDR (0x03018000)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_MESH_X_Y_ORIENTATION_REG_OFFSET (0x00000008)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_MESH_X_Y_ORIENTATION_REG_ADDR (0x03018008)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_ENDPOINT_ID_REG_OFFSET (0x00000010)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_ENDPOINT_ID_REG_ADDR (0x03018010)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_X_Y_DEFAULT_REG_OFFSET (0x00000018)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_X_Y_DEFAULT_REG_ADDR (0x03018018)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_MESH_X_Y_ORIENTATION_DEFAULT_REG_OFFSET (0x00000020)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_MESH_X_Y_ORIENTATION_DEFAULT_REG_ADDR (0x03018020)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_ENDPOINT_ID_DEFAULT_REG_OFFSET (0x00000028)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_ENDPOINT_ID_DEFAULT_REG_ADDR (0x03018028)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_FENCE_ENABLE_REG_OFFSET (0x00000030)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_FENCE_ENABLE_REG_ADDR (0x03018030)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_SECURE_GROUP_ID_REG_OFFSET (0x00000038)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_SECURE_GROUP_ID_REG_ADDR (0x03018038)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_RANGE_START_0_REG_OFFSET (0x00000040)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_RANGE_START_0_REG_ADDR (0x03018040)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_RANGE_END_0_REG_OFFSET (0x00000048)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_RANGE_END_0_REG_ADDR (0x03018048)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_RANGE_START_1_REG_OFFSET (0x00000050)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_RANGE_START_1_REG_ADDR (0x03018050)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_RANGE_END_1_REG_OFFSET (0x00000058)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_RANGE_END_1_REG_ADDR (0x03018058)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_RANGE_START_2_REG_OFFSET (0x00000060)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_RANGE_START_2_REG_ADDR (0x03018060)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_RANGE_END_2_REG_OFFSET (0x00000068)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_RANGE_END_2_REG_ADDR (0x03018068)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_RANGE_START_3_REG_OFFSET (0x00000070)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_RANGE_START_3_REG_ADDR (0x03018070)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_RANGE_END_3_REG_OFFSET (0x00000078)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_RANGE_END_3_REG_ADDR (0x03018078)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_RANGE_START_4_REG_OFFSET (0x00000080)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_RANGE_START_4_REG_ADDR (0x03018080)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_RANGE_END_4_REG_OFFSET (0x00000088)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_RANGE_END_4_REG_ADDR (0x03018088)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_RANGE_START_5_REG_OFFSET (0x00000090)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_RANGE_START_5_REG_ADDR (0x03018090)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_RANGE_END_5_REG_OFFSET (0x00000098)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_RANGE_END_5_REG_ADDR (0x03018098)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_RANGE_START_6_REG_OFFSET (0x000000A0)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_RANGE_START_6_REG_ADDR (0x030180A0)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_RANGE_END_6_REG_OFFSET (0x000000A8)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_RANGE_END_6_REG_ADDR (0x030180A8)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_RANGE_START_7_REG_OFFSET (0x000000B0)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_RANGE_START_7_REG_ADDR (0x030180B0)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_RANGE_END_7_REG_OFFSET (0x000000B8)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_RANGE_END_7_REG_ADDR (0x030180B8)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_ATTRIBUTE_0__REG_OFFSET (0x000000C0)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_ATTRIBUTE_0__REG_ADDR (0x030180C0)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_ATTRIBUTE_1__REG_OFFSET (0x000000C8)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_ATTRIBUTE_1__REG_ADDR (0x030180C8)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_ATTRIBUTE_2__REG_OFFSET (0x000000D0)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_ATTRIBUTE_2__REG_ADDR (0x030180D0)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_ATTRIBUTE_3__REG_OFFSET (0x000000D8)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_ATTRIBUTE_3__REG_ADDR (0x030180D8)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_ATTRIBUTE_4__REG_OFFSET (0x000000E0)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_ATTRIBUTE_4__REG_ADDR (0x030180E0)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_ATTRIBUTE_5__REG_OFFSET (0x000000E8)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_ATTRIBUTE_5__REG_ADDR (0x030180E8)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_ATTRIBUTE_6__REG_OFFSET (0x000000F0)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_ATTRIBUTE_6__REG_ADDR (0x030180F0)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_ATTRIBUTE_7__REG_OFFSET (0x000000F8)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_ATTRIBUTE_7__REG_ADDR (0x030180F8)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_MASTER_LEVEL_REG_OFFSET (0x00000100)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_MASTER_LEVEL_REG_ADDR (0x03018100)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_VIOLATION_FIFO_STATUS_REG_OFFSET (0x00000108)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_VIOLATION_FIFO_STATUS_REG_ADDR (0x03018108)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_VIOLATION_FIFO_RDDATA_REG_OFFSET (0x00000110)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_VIOLATION_FIFO_RDDATA_REG_ADDR (0x03018110)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_DEFAULT_RANGE_ATTRIBUTE_REG_OFFSET (0x00000118)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_DEFAULT_RANGE_ATTRIBUTE_REG_ADDR (0x03018118)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_DEFAULT_RANGE_START_REG_OFFSET (0x00000120)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_DEFAULT_RANGE_START_REG_ADDR (0x03018120)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_DEFAULT_RANGE_END_REG_OFFSET (0x00000128)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_DEFAULT_RANGE_END_REG_ADDR (0x03018128)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_POP_VIOLATION_FIFO_REG_OFFSET (0x00000130)
#define SMN_SMN_SLV_NOC_SEC_BLOCK_SMN_NOC_SEC_POP_VIOLATION_FIFO_REG_ADDR (0x03018130)

//==============================================================================
// Addresses for Address Map: smn_slv_d2d_block
//==============================================================================

#define SMN_SMN_SLV_D2D_BLOCK_REG_MAP_BASE_ADDR (0x03019000)
#define SMN_SMN_SLV_D2D_BLOCK_REG_MAP_SIZE (0x00000050)

#define SMN_SMN_SLV_D2D_BLOCK_SMN_SLV_D2D_BAR_BASE_0__REG_OFFSET (0x00000000)
#define SMN_SMN_SLV_D2D_BLOCK_SMN_SLV_D2D_BAR_BASE_0__REG_ADDR (0x03019000)
#define SMN_SMN_SLV_D2D_BLOCK_SMN_SLV_D2D_BAR_BASE_1__REG_OFFSET (0x00000008)
#define SMN_SMN_SLV_D2D_BLOCK_SMN_SLV_D2D_BAR_BASE_1__REG_ADDR (0x03019008)
#define SMN_SMN_SLV_D2D_BLOCK_SMN_SLV_D2D_BAR_BASE_2__REG_OFFSET (0x00000010)
#define SMN_SMN_SLV_D2D_BLOCK_SMN_SLV_D2D_BAR_BASE_2__REG_ADDR (0x03019010)
#define SMN_SMN_SLV_D2D_BLOCK_SMN_SLV_D2D_BAR_BASE_3__REG_OFFSET (0x00000018)
#define SMN_SMN_SLV_D2D_BLOCK_SMN_SLV_D2D_BAR_BASE_3__REG_ADDR (0x03019018)
#define SMN_SMN_SLV_D2D_BLOCK_SMN_SLV_D2D_BAR_LIMIT_0__REG_OFFSET (0x00000020)
#define SMN_SMN_SLV_D2D_BLOCK_SMN_SLV_D2D_BAR_LIMIT_0__REG_ADDR (0x03019020)
#define SMN_SMN_SLV_D2D_BLOCK_SMN_SLV_D2D_BAR_LIMIT_1__REG_OFFSET (0x00000028)
#define SMN_SMN_SLV_D2D_BLOCK_SMN_SLV_D2D_BAR_LIMIT_1__REG_ADDR (0x03019028)
#define SMN_SMN_SLV_D2D_BLOCK_SMN_SLV_D2D_BAR_LIMIT_2__REG_OFFSET (0x00000030)
#define SMN_SMN_SLV_D2D_BLOCK_SMN_SLV_D2D_BAR_LIMIT_2__REG_ADDR (0x03019030)
#define SMN_SMN_SLV_D2D_BLOCK_SMN_SLV_D2D_BAR_LIMIT_3__REG_OFFSET (0x00000038)
#define SMN_SMN_SLV_D2D_BLOCK_SMN_SLV_D2D_BAR_LIMIT_3__REG_ADDR (0x03019038)
#define SMN_SMN_SLV_D2D_BLOCK_SMN_SLV_D2D_SS_BAR_ADDR_REG_OFFSET (0x00000040)
#define SMN_SMN_SLV_D2D_BLOCK_SMN_SLV_D2D_SS_BAR_ADDR_REG_ADDR (0x03019040)
#define SMN_SMN_SLV_D2D_BLOCK_SMN_SLV_D2D_DTB_SEL_REG_OFFSET (0x00000048)
#define SMN_SMN_SLV_D2D_BLOCK_SMN_SLV_D2D_DTB_SEL_REG_ADDR (0x03019048)

//==============================================================================
// Addresses for Address Map: tt_neo_awm_wrap
//==============================================================================

#define TT_NEO_AWM_WRAP_REG_MAP_BASE_ADDR (0x03020000)
#define TT_NEO_AWM_WRAP_REG_MAP_SIZE (0x00000AC0)

//==============================================================================
// Addresses for Address Map: awm
//==============================================================================

#define TT_NEO_AWM_WRAP_AWM_REG_MAP_BASE_ADDR (0x03020000)
#define TT_NEO_AWM_WRAP_AWM_REG_MAP_SIZE (0x000004E2)

//==============================================================================
// Addresses for Address Map: GLOBAL_a
//==============================================================================

#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_REG_MAP_BASE_ADDR (0x03020000)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_REG_MAP_SIZE (0x000000AA)

#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_RESOURCE_CONFIGURATION_ENABLES_REG_OFFSET (0x00000000)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_RESOURCE_CONFIGURATION_ENABLES_REG_ADDR (0x03020000)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_DYNAMIC_SCHEME_0_REG_OFFSET (0x00000004)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_DYNAMIC_SCHEME_0_REG_ADDR (0x03020004)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_DYNAMIC_SCHEME_1_REG_OFFSET (0x00000008)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_DYNAMIC_SCHEME_1_REG_ADDR (0x03020008)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_DYNAMIC_SCHEME_2_REG_OFFSET (0x0000000C)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_DYNAMIC_SCHEME_2_REG_ADDR (0x0302000C)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_DYNAMIC_SCHEME_3_REG_OFFSET (0x00000010)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_DYNAMIC_SCHEME_3_REG_ADDR (0x03020010)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_DYNAMIC_SCHEME_4_REG_OFFSET (0x00000014)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_DYNAMIC_SCHEME_4_REG_ADDR (0x03020014)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_DYNAMIC_SCHEME_5_REG_OFFSET (0x00000018)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_DYNAMIC_SCHEME_5_REG_ADDR (0x03020018)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_FCW_INT_BOUND_REG_OFFSET (0x0000001C)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_FCW_INT_BOUND_REG_ADDR (0x0302001C)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_FCW_FRAC_UPPERBOUND_REG_OFFSET (0x00000020)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_FCW_FRAC_UPPERBOUND_REG_ADDR (0x03020020)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_FCW_FRAC_LOWERBOUND_REG_OFFSET (0x00000024)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_FCW_FRAC_LOWERBOUND_REG_ADDR (0x03020024)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_REG_UPDATE_REG_OFFSET (0x00000028)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_REG_UPDATE_REG_ADDR (0x03020028)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_MEAS_CONFIG_REG_OFFSET (0x00000034)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_MEAS_CONFIG_REG_ADDR (0x03020034)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_MEAS_DURATION0_REG_OFFSET (0x00000038)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_MEAS_DURATION0_REG_ADDR (0x03020038)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_MEAS_DURATION1_REG_OFFSET (0x0000003C)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_MEAS_DURATION1_REG_ADDR (0x0302003C)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_MEAS_STATUS_REG_OFFSET (0x00000040)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_MEAS_STATUS_REG_ADDR (0x03020040)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_EXT_FREQ_REG_OFFSET (0x00000044)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_EXT_FREQ_REG_ADDR (0x03020044)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_EXT_REF_REG_OFFSET (0x00000048)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_EXT_REF_REG_ADDR (0x03020048)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_EXT_DROOP_DUR0_REG_OFFSET (0x0000004C)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_EXT_DROOP_DUR0_REG_ADDR (0x0302004C)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_EXT_DROOP_DUR1_REG_OFFSET (0x00000050)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_EXT_DROOP_DUR1_REG_ADDR (0x03020050)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_EXT_DROOP_DUR2_REG_OFFSET (0x00000054)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_EXT_DROOP_DUR2_REG_ADDR (0x03020054)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_EXT_DROOP_DUR3_REG_OFFSET (0x00000058)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_EXT_DROOP_DUR3_REG_ADDR (0x03020058)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_EXT_DROOP_TRAN01_REG_OFFSET (0x0000005C)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_EXT_DROOP_TRAN01_REG_ADDR (0x0302005C)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_EXT_DROOP_TRAN23_REG_OFFSET (0x00000060)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_EXT_DROOP_TRAN23_REG_ADDR (0x03020060)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_EXT_FLOOR_LOOPS_REG_OFFSET (0x00000064)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_EXT_FLOOR_LOOPS_REG_ADDR (0x03020064)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_EXT_FLOOR1_DURATION0_REG_OFFSET (0x00000068)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_EXT_FLOOR1_DURATION0_REG_ADDR (0x03020068)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_EXT_FLOOR2_DURATION0_REG_OFFSET (0x0000006C)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_EXT_FLOOR2_DURATION0_REG_ADDR (0x0302006C)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_EXT_FLOOR3_DURATION0_REG_OFFSET (0x00000070)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_EXT_FLOOR3_DURATION0_REG_ADDR (0x03020070)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_EXT_FLOOR1_DURATION1_REG_OFFSET (0x00000074)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_EXT_FLOOR1_DURATION1_REG_ADDR (0x03020074)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_EXT_FLOOR2_DURATION1_REG_OFFSET (0x00000078)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_EXT_FLOOR2_DURATION1_REG_ADDR (0x03020078)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_EXT_FLOOR3_DURATION1_REG_OFFSET (0x0000007C)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_EXT_FLOOR3_DURATION1_REG_ADDR (0x0302007C)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_EXT_FLOOR1_DURATION2_REG_OFFSET (0x00000080)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_EXT_FLOOR1_DURATION2_REG_ADDR (0x03020080)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_EXT_FLOOR2_DURATION2_REG_OFFSET (0x00000084)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_EXT_FLOOR2_DURATION2_REG_ADDR (0x03020084)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_EXT_FLOOR3_DURATION2_REG_OFFSET (0x00000088)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_EXT_FLOOR3_DURATION2_REG_ADDR (0x03020088)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_EXT_SAFETY_DURATION0_REG_OFFSET (0x0000008C)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_EXT_SAFETY_DURATION0_REG_ADDR (0x0302008C)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_EXT_SAFETY_DURATION1_REG_OFFSET (0x00000090)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_EXT_SAFETY_DURATION1_REG_ADDR (0x03020090)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_EXT_SAFETY_DURATION2_REG_OFFSET (0x00000094)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_EXT_SAFETY_DURATION2_REG_ADDR (0x03020094)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_LOCK_MONITOR_0_REG_OFFSET (0x0000009C)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_LOCK_MONITOR_0_REG_ADDR (0x0302009C)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_LOCK_MONITOR_1_REG_OFFSET (0x000000A0)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_LOCK_MONITOR_1_REG_ADDR (0x030200A0)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_LOCK_MONITOR_2_REG_OFFSET (0x000000A4)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_LOCK_MONITOR_2_REG_ADDR (0x030200A4)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_DROOP_PAUSE_REG_OFFSET (0x000000A8)
#define TT_NEO_AWM_WRAP_AWM_GLOBAL_A_DROOP_PAUSE_REG_ADDR (0x030200A8)

//==============================================================================
// Addresses for Address Map: FREQUENCY0_a
//==============================================================================

#define TT_NEO_AWM_WRAP_AWM_FREQUENCY0_A_REG_MAP_BASE_ADDR (0x03020100)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY0_A_REG_MAP_SIZE (0x0000001E)

#define TT_NEO_AWM_WRAP_AWM_FREQUENCY0_A_FCW_INT0_REG_OFFSET (0x00000000)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY0_A_FCW_INT0_REG_ADDR (0x03020100)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY0_A_FCW_INT1_REG_OFFSET (0x00000004)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY0_A_FCW_INT1_REG_ADDR (0x03020104)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY0_A_FCW_FRAC_REG_OFFSET (0x00000008)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY0_A_FCW_FRAC_REG_ADDR (0x03020108)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY0_A_FCW_FRAC1_REG_OFFSET (0x0000000C)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY0_A_FCW_FRAC1_REG_ADDR (0x0302010C)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY0_A_FCW_FRAC2_REG_OFFSET (0x00000010)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY0_A_FCW_FRAC2_REG_ADDR (0x03020110)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY0_A_FCW_FRAC3_REG_OFFSET (0x00000014)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY0_A_FCW_FRAC3_REG_ADDR (0x03020114)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY0_A_PREDIV_REG_OFFSET (0x00000018)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY0_A_PREDIV_REG_ADDR (0x03020118)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY0_A_FREQ_ACQ_ENABLES_REG_OFFSET (0x0000001C)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY0_A_FREQ_ACQ_ENABLES_REG_ADDR (0x0302011C)

//==============================================================================
// Addresses for Address Map: FREQUENCY1_a
//==============================================================================

#define TT_NEO_AWM_WRAP_AWM_FREQUENCY1_A_REG_MAP_BASE_ADDR (0x03020140)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY1_A_REG_MAP_SIZE (0x0000001E)

#define TT_NEO_AWM_WRAP_AWM_FREQUENCY1_A_FCW_INT0_REG_OFFSET (0x00000000)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY1_A_FCW_INT0_REG_ADDR (0x03020140)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY1_A_FCW_INT1_REG_OFFSET (0x00000004)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY1_A_FCW_INT1_REG_ADDR (0x03020144)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY1_A_FCW_FRAC_REG_OFFSET (0x00000008)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY1_A_FCW_FRAC_REG_ADDR (0x03020148)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY1_A_FCW_FRAC1_REG_OFFSET (0x0000000C)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY1_A_FCW_FRAC1_REG_ADDR (0x0302014C)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY1_A_FCW_FRAC2_REG_OFFSET (0x00000010)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY1_A_FCW_FRAC2_REG_ADDR (0x03020150)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY1_A_FCW_FRAC3_REG_OFFSET (0x00000014)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY1_A_FCW_FRAC3_REG_ADDR (0x03020154)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY1_A_PREDIV_REG_OFFSET (0x00000018)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY1_A_PREDIV_REG_ADDR (0x03020158)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY1_A_FREQ_ACQ_ENABLES_REG_OFFSET (0x0000001C)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY1_A_FREQ_ACQ_ENABLES_REG_ADDR (0x0302015C)

//==============================================================================
// Addresses for Address Map: FREQUENCY2_a
//==============================================================================

#define TT_NEO_AWM_WRAP_AWM_FREQUENCY2_A_REG_MAP_BASE_ADDR (0x03020180)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY2_A_REG_MAP_SIZE (0x0000001E)

#define TT_NEO_AWM_WRAP_AWM_FREQUENCY2_A_FCW_INT0_REG_OFFSET (0x00000000)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY2_A_FCW_INT0_REG_ADDR (0x03020180)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY2_A_FCW_INT1_REG_OFFSET (0x00000004)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY2_A_FCW_INT1_REG_ADDR (0x03020184)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY2_A_FCW_FRAC_REG_OFFSET (0x00000008)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY2_A_FCW_FRAC_REG_ADDR (0x03020188)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY2_A_FCW_FRAC1_REG_OFFSET (0x0000000C)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY2_A_FCW_FRAC1_REG_ADDR (0x0302018C)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY2_A_FCW_FRAC2_REG_OFFSET (0x00000010)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY2_A_FCW_FRAC2_REG_ADDR (0x03020190)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY2_A_FCW_FRAC3_REG_OFFSET (0x00000014)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY2_A_FCW_FRAC3_REG_ADDR (0x03020194)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY2_A_PREDIV_REG_OFFSET (0x00000018)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY2_A_PREDIV_REG_ADDR (0x03020198)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY2_A_FREQ_ACQ_ENABLES_REG_OFFSET (0x0000001C)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY2_A_FREQ_ACQ_ENABLES_REG_ADDR (0x0302019C)

//==============================================================================
// Addresses for Address Map: FREQUENCY3_a
//==============================================================================

#define TT_NEO_AWM_WRAP_AWM_FREQUENCY3_A_REG_MAP_BASE_ADDR (0x030201C0)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY3_A_REG_MAP_SIZE (0x0000001E)

#define TT_NEO_AWM_WRAP_AWM_FREQUENCY3_A_FCW_INT0_REG_OFFSET (0x00000000)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY3_A_FCW_INT0_REG_ADDR (0x030201C0)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY3_A_FCW_INT1_REG_OFFSET (0x00000004)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY3_A_FCW_INT1_REG_ADDR (0x030201C4)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY3_A_FCW_FRAC_REG_OFFSET (0x00000008)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY3_A_FCW_FRAC_REG_ADDR (0x030201C8)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY3_A_FCW_FRAC1_REG_OFFSET (0x0000000C)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY3_A_FCW_FRAC1_REG_ADDR (0x030201CC)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY3_A_FCW_FRAC2_REG_OFFSET (0x00000010)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY3_A_FCW_FRAC2_REG_ADDR (0x030201D0)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY3_A_FCW_FRAC3_REG_OFFSET (0x00000014)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY3_A_FCW_FRAC3_REG_ADDR (0x030201D4)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY3_A_PREDIV_REG_OFFSET (0x00000018)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY3_A_PREDIV_REG_ADDR (0x030201D8)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY3_A_FREQ_ACQ_ENABLES_REG_OFFSET (0x0000001C)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY3_A_FREQ_ACQ_ENABLES_REG_ADDR (0x030201DC)

//==============================================================================
// Addresses for Address Map: FREQUENCY4_a
//==============================================================================

#define TT_NEO_AWM_WRAP_AWM_FREQUENCY4_A_REG_MAP_BASE_ADDR (0x03020200)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY4_A_REG_MAP_SIZE (0x0000001E)

#define TT_NEO_AWM_WRAP_AWM_FREQUENCY4_A_FCW_INT0_REG_OFFSET (0x00000000)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY4_A_FCW_INT0_REG_ADDR (0x03020200)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY4_A_FCW_INT1_REG_OFFSET (0x00000004)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY4_A_FCW_INT1_REG_ADDR (0x03020204)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY4_A_FCW_FRAC_REG_OFFSET (0x00000008)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY4_A_FCW_FRAC_REG_ADDR (0x03020208)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY4_A_FCW_FRAC1_REG_OFFSET (0x0000000C)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY4_A_FCW_FRAC1_REG_ADDR (0x0302020C)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY4_A_FCW_FRAC2_REG_OFFSET (0x00000010)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY4_A_FCW_FRAC2_REG_ADDR (0x03020210)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY4_A_FCW_FRAC3_REG_OFFSET (0x00000014)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY4_A_FCW_FRAC3_REG_ADDR (0x03020214)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY4_A_PREDIV_REG_OFFSET (0x00000018)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY4_A_PREDIV_REG_ADDR (0x03020218)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY4_A_FREQ_ACQ_ENABLES_REG_OFFSET (0x0000001C)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY4_A_FREQ_ACQ_ENABLES_REG_ADDR (0x0302021C)

//==============================================================================
// Addresses for Address Map: FREQUENCY5_a
//==============================================================================

#define TT_NEO_AWM_WRAP_AWM_FREQUENCY5_A_REG_MAP_BASE_ADDR (0x03020240)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY5_A_REG_MAP_SIZE (0x0000001E)

#define TT_NEO_AWM_WRAP_AWM_FREQUENCY5_A_FCW_INT0_REG_OFFSET (0x00000000)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY5_A_FCW_INT0_REG_ADDR (0x03020240)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY5_A_FCW_INT1_REG_OFFSET (0x00000004)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY5_A_FCW_INT1_REG_ADDR (0x03020244)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY5_A_FCW_FRAC_REG_OFFSET (0x00000008)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY5_A_FCW_FRAC_REG_ADDR (0x03020248)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY5_A_FCW_FRAC1_REG_OFFSET (0x0000000C)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY5_A_FCW_FRAC1_REG_ADDR (0x0302024C)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY5_A_FCW_FRAC2_REG_OFFSET (0x00000010)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY5_A_FCW_FRAC2_REG_ADDR (0x03020250)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY5_A_FCW_FRAC3_REG_OFFSET (0x00000014)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY5_A_FCW_FRAC3_REG_ADDR (0x03020254)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY5_A_PREDIV_REG_OFFSET (0x00000018)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY5_A_PREDIV_REG_ADDR (0x03020258)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY5_A_FREQ_ACQ_ENABLES_REG_OFFSET (0x0000001C)
#define TT_NEO_AWM_WRAP_AWM_FREQUENCY5_A_FREQ_ACQ_ENABLES_REG_ADDR (0x0302025C)

//==============================================================================
// Addresses for Address Map: CGM0_a
//==============================================================================

#define TT_NEO_AWM_WRAP_AWM_CGM0_A_REG_MAP_BASE_ADDR (0x03020280)
#define TT_NEO_AWM_WRAP_AWM_CGM0_A_REG_MAP_SIZE (0x00000062)

#define TT_NEO_AWM_WRAP_AWM_CGM0_A_ENABLES_REG_OFFSET (0x00000000)
#define TT_NEO_AWM_WRAP_AWM_CGM0_A_ENABLES_REG_ADDR (0x03020280)
#define TT_NEO_AWM_WRAP_AWM_CGM0_A_OPEN_LOOP_REG_OFFSET (0x00000004)
#define TT_NEO_AWM_WRAP_AWM_CGM0_A_OPEN_LOOP_REG_ADDR (0x03020284)
#define TT_NEO_AWM_WRAP_AWM_CGM0_A_DM0_READ_REG_OFFSET (0x00000020)
#define TT_NEO_AWM_WRAP_AWM_CGM0_A_DM0_READ_REG_ADDR (0x030202A0)
#define TT_NEO_AWM_WRAP_AWM_CGM0_A_DM1_READ_REG_OFFSET (0x00000024)
#define TT_NEO_AWM_WRAP_AWM_CGM0_A_DM1_READ_REG_ADDR (0x030202A4)
#define TT_NEO_AWM_WRAP_AWM_CGM0_A_DM2_READ_REG_OFFSET (0x00000028)
#define TT_NEO_AWM_WRAP_AWM_CGM0_A_DM2_READ_REG_ADDR (0x030202A8)
#define TT_NEO_AWM_WRAP_AWM_CGM0_A_DM3_READ_REG_OFFSET (0x0000002C)
#define TT_NEO_AWM_WRAP_AWM_CGM0_A_DM3_READ_REG_ADDR (0x030202AC)
#define TT_NEO_AWM_WRAP_AWM_CGM0_A_CGM_STATUS_REG_OFFSET (0x00000030)
#define TT_NEO_AWM_WRAP_AWM_CGM0_A_CGM_STATUS_REG_ADDR (0x030202B0)
#define TT_NEO_AWM_WRAP_AWM_CGM0_A_DM0_CONFIG_REG_OFFSET (0x00000034)
#define TT_NEO_AWM_WRAP_AWM_CGM0_A_DM0_CONFIG_REG_ADDR (0x030202B4)
#define TT_NEO_AWM_WRAP_AWM_CGM0_A_FREQ_MONITOR_CONFIG_REG_OFFSET (0x00000054)
#define TT_NEO_AWM_WRAP_AWM_CGM0_A_FREQ_MONITOR_CONFIG_REG_ADDR (0x030202D4)
#define TT_NEO_AWM_WRAP_AWM_CGM0_A_FREQ_MONITOR_COUNT_REG_OFFSET (0x00000058)
#define TT_NEO_AWM_WRAP_AWM_CGM0_A_FREQ_MONITOR_COUNT_REG_ADDR (0x030202D8)
#define TT_NEO_AWM_WRAP_AWM_CGM0_A_DCO_CODE_INST_READ_REG_OFFSET (0x00000060)
#define TT_NEO_AWM_WRAP_AWM_CGM0_A_DCO_CODE_INST_READ_REG_ADDR (0x030202E0)

//==============================================================================
// Addresses for Address Map: CGM1_a
//==============================================================================

#define TT_NEO_AWM_WRAP_AWM_CGM1_A_REG_MAP_BASE_ADDR (0x03020380)
#define TT_NEO_AWM_WRAP_AWM_CGM1_A_REG_MAP_SIZE (0x00000062)

#define TT_NEO_AWM_WRAP_AWM_CGM1_A_ENABLES_REG_OFFSET (0x00000000)
#define TT_NEO_AWM_WRAP_AWM_CGM1_A_ENABLES_REG_ADDR (0x03020380)
#define TT_NEO_AWM_WRAP_AWM_CGM1_A_OPEN_LOOP_REG_OFFSET (0x00000004)
#define TT_NEO_AWM_WRAP_AWM_CGM1_A_OPEN_LOOP_REG_ADDR (0x03020384)
#define TT_NEO_AWM_WRAP_AWM_CGM1_A_DM0_READ_REG_OFFSET (0x00000020)
#define TT_NEO_AWM_WRAP_AWM_CGM1_A_DM0_READ_REG_ADDR (0x030203A0)
#define TT_NEO_AWM_WRAP_AWM_CGM1_A_DM1_READ_REG_OFFSET (0x00000024)
#define TT_NEO_AWM_WRAP_AWM_CGM1_A_DM1_READ_REG_ADDR (0x030203A4)
#define TT_NEO_AWM_WRAP_AWM_CGM1_A_DM2_READ_REG_OFFSET (0x00000028)
#define TT_NEO_AWM_WRAP_AWM_CGM1_A_DM2_READ_REG_ADDR (0x030203A8)
#define TT_NEO_AWM_WRAP_AWM_CGM1_A_DM3_READ_REG_OFFSET (0x0000002C)
#define TT_NEO_AWM_WRAP_AWM_CGM1_A_DM3_READ_REG_ADDR (0x030203AC)
#define TT_NEO_AWM_WRAP_AWM_CGM1_A_CGM_STATUS_REG_OFFSET (0x00000030)
#define TT_NEO_AWM_WRAP_AWM_CGM1_A_CGM_STATUS_REG_ADDR (0x030203B0)
#define TT_NEO_AWM_WRAP_AWM_CGM1_A_DM0_CONFIG_REG_OFFSET (0x00000034)
#define TT_NEO_AWM_WRAP_AWM_CGM1_A_DM0_CONFIG_REG_ADDR (0x030203B4)
#define TT_NEO_AWM_WRAP_AWM_CGM1_A_FREQ_MONITOR_CONFIG_REG_OFFSET (0x00000054)
#define TT_NEO_AWM_WRAP_AWM_CGM1_A_FREQ_MONITOR_CONFIG_REG_ADDR (0x030203D4)
#define TT_NEO_AWM_WRAP_AWM_CGM1_A_FREQ_MONITOR_COUNT_REG_OFFSET (0x00000058)
#define TT_NEO_AWM_WRAP_AWM_CGM1_A_FREQ_MONITOR_COUNT_REG_ADDR (0x030203D8)
#define TT_NEO_AWM_WRAP_AWM_CGM1_A_DCO_CODE_INST_READ_REG_OFFSET (0x00000060)
#define TT_NEO_AWM_WRAP_AWM_CGM1_A_DCO_CODE_INST_READ_REG_ADDR (0x030203E0)

//==============================================================================
// Addresses for Address Map: CGM2_a
//==============================================================================

#define TT_NEO_AWM_WRAP_AWM_CGM2_A_REG_MAP_BASE_ADDR (0x03020480)
#define TT_NEO_AWM_WRAP_AWM_CGM2_A_REG_MAP_SIZE (0x00000062)

#define TT_NEO_AWM_WRAP_AWM_CGM2_A_ENABLES_REG_OFFSET (0x00000000)
#define TT_NEO_AWM_WRAP_AWM_CGM2_A_ENABLES_REG_ADDR (0x03020480)
#define TT_NEO_AWM_WRAP_AWM_CGM2_A_OPEN_LOOP_REG_OFFSET (0x00000004)
#define TT_NEO_AWM_WRAP_AWM_CGM2_A_OPEN_LOOP_REG_ADDR (0x03020484)
#define TT_NEO_AWM_WRAP_AWM_CGM2_A_DM0_READ_REG_OFFSET (0x00000020)
#define TT_NEO_AWM_WRAP_AWM_CGM2_A_DM0_READ_REG_ADDR (0x030204A0)
#define TT_NEO_AWM_WRAP_AWM_CGM2_A_DM1_READ_REG_OFFSET (0x00000024)
#define TT_NEO_AWM_WRAP_AWM_CGM2_A_DM1_READ_REG_ADDR (0x030204A4)
#define TT_NEO_AWM_WRAP_AWM_CGM2_A_DM2_READ_REG_OFFSET (0x00000028)
#define TT_NEO_AWM_WRAP_AWM_CGM2_A_DM2_READ_REG_ADDR (0x030204A8)
#define TT_NEO_AWM_WRAP_AWM_CGM2_A_DM3_READ_REG_OFFSET (0x0000002C)
#define TT_NEO_AWM_WRAP_AWM_CGM2_A_DM3_READ_REG_ADDR (0x030204AC)
#define TT_NEO_AWM_WRAP_AWM_CGM2_A_CGM_STATUS_REG_OFFSET (0x00000030)
#define TT_NEO_AWM_WRAP_AWM_CGM2_A_CGM_STATUS_REG_ADDR (0x030204B0)
#define TT_NEO_AWM_WRAP_AWM_CGM2_A_DM0_CONFIG_REG_OFFSET (0x00000034)
#define TT_NEO_AWM_WRAP_AWM_CGM2_A_DM0_CONFIG_REG_ADDR (0x030204B4)
#define TT_NEO_AWM_WRAP_AWM_CGM2_A_FREQ_MONITOR_CONFIG_REG_OFFSET (0x00000054)
#define TT_NEO_AWM_WRAP_AWM_CGM2_A_FREQ_MONITOR_CONFIG_REG_ADDR (0x030204D4)
#define TT_NEO_AWM_WRAP_AWM_CGM2_A_FREQ_MONITOR_COUNT_REG_OFFSET (0x00000058)
#define TT_NEO_AWM_WRAP_AWM_CGM2_A_FREQ_MONITOR_COUNT_REG_ADDR (0x030204D8)
#define TT_NEO_AWM_WRAP_AWM_CGM2_A_DCO_CODE_INST_READ_REG_OFFSET (0x00000060)
#define TT_NEO_AWM_WRAP_AWM_CGM2_A_DCO_CODE_INST_READ_REG_ADDR (0x030204E0)

//==============================================================================
// Addresses for Address Map: droop_0
//==============================================================================

#define TT_NEO_AWM_WRAP_DROOP_0_REG_MAP_BASE_ADDR (0x03020500)
#define TT_NEO_AWM_WRAP_DROOP_0_REG_MAP_SIZE (0x000000F2)

#define TT_NEO_AWM_WRAP_DROOP_0_ENABLES_REG_OFFSET (0x00000000)
#define TT_NEO_AWM_WRAP_DROOP_0_ENABLES_REG_ADDR (0x03020500)
#define TT_NEO_AWM_WRAP_DROOP_0_SAMPLE_STROBE_REG_OFFSET (0x00000004)
#define TT_NEO_AWM_WRAP_DROOP_0_SAMPLE_STROBE_REG_ADDR (0x03020504)
#define TT_NEO_AWM_WRAP_DROOP_0_TARGET_MONITOR_CODE_REG_OFFSET (0x00000008)
#define TT_NEO_AWM_WRAP_DROOP_0_TARGET_MONITOR_CODE_REG_ADDR (0x03020508)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_REG_OFFSET (0x0000000C)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_REG_ADDR (0x0302050C)
#define TT_NEO_AWM_WRAP_DROOP_0_MEAS_DURATION0_REG_OFFSET (0x00000010)
#define TT_NEO_AWM_WRAP_DROOP_0_MEAS_DURATION0_REG_ADDR (0x03020510)
#define TT_NEO_AWM_WRAP_DROOP_0_MEAS_DURATION1_REG_OFFSET (0x00000014)
#define TT_NEO_AWM_WRAP_DROOP_0_MEAS_DURATION1_REG_ADDR (0x03020514)
#define TT_NEO_AWM_WRAP_DROOP_0_LONG_TERM_MAX_CODE_REG_OFFSET (0x00000018)
#define TT_NEO_AWM_WRAP_DROOP_0_LONG_TERM_MAX_CODE_REG_ADDR (0x03020518)
#define TT_NEO_AWM_WRAP_DROOP_0_LONG_TERM_MIN_CODE_REG_OFFSET (0x0000001C)
#define TT_NEO_AWM_WRAP_DROOP_0_LONG_TERM_MIN_CODE_REG_ADDR (0x0302051C)
#define TT_NEO_AWM_WRAP_DROOP_0_EXT_DROOP_DUR0_REG_OFFSET (0x00000020)
#define TT_NEO_AWM_WRAP_DROOP_0_EXT_DROOP_DUR0_REG_ADDR (0x03020520)
#define TT_NEO_AWM_WRAP_DROOP_0_EXT_DROOP_DUR1_REG_OFFSET (0x00000024)
#define TT_NEO_AWM_WRAP_DROOP_0_EXT_DROOP_DUR1_REG_ADDR (0x03020524)
#define TT_NEO_AWM_WRAP_DROOP_0_EXT_DROOP_DUR2_REG_OFFSET (0x00000028)
#define TT_NEO_AWM_WRAP_DROOP_0_EXT_DROOP_DUR2_REG_ADDR (0x03020528)
#define TT_NEO_AWM_WRAP_DROOP_0_EXT_DROOP_DUR3_REG_OFFSET (0x0000002C)
#define TT_NEO_AWM_WRAP_DROOP_0_EXT_DROOP_DUR3_REG_ADDR (0x0302052C)
#define TT_NEO_AWM_WRAP_DROOP_0_EXT_DROOP_TRAN_01_REG_OFFSET (0x00000030)
#define TT_NEO_AWM_WRAP_DROOP_0_EXT_DROOP_TRAN_01_REG_ADDR (0x03020530)
#define TT_NEO_AWM_WRAP_DROOP_0_EXT_DROOP_TRAN_23_REG_OFFSET (0x00000034)
#define TT_NEO_AWM_WRAP_DROOP_0_EXT_DROOP_TRAN_23_REG_ADDR (0x03020534)
#define TT_NEO_AWM_WRAP_DROOP_0_FORCE_REG_OFFSET (0x00000038)
#define TT_NEO_AWM_WRAP_DROOP_0_FORCE_REG_ADDR (0x03020538)
#define TT_NEO_AWM_WRAP_DROOP_0_SAMPLED_AVG_MONITOR_REG_OFFSET (0x0000003C)
#define TT_NEO_AWM_WRAP_DROOP_0_SAMPLED_AVG_MONITOR_REG_ADDR (0x0302053C)
#define TT_NEO_AWM_WRAP_DROOP_0_SAMPLED_DROOP_REG_OFFSET (0x00000040)
#define TT_NEO_AWM_WRAP_DROOP_0_SAMPLED_DROOP_REG_ADDR (0x03020540)
#define TT_NEO_AWM_WRAP_DROOP_0_SAMPLED_MONITOR_REG_OFFSET (0x00000044)
#define TT_NEO_AWM_WRAP_DROOP_0_SAMPLED_MONITOR_REG_ADDR (0x03020544)
#define TT_NEO_AWM_WRAP_DROOP_0_SAMPLED_DELAY_REG_OFFSET (0x00000048)
#define TT_NEO_AWM_WRAP_DROOP_0_SAMPLED_DELAY_REG_ADDR (0x03020548)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_0_LW_REG_OFFSET (0x0000004C)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_0_LW_REG_ADDR (0x0302054C)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_0_HW_REG_OFFSET (0x00000050)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_0_HW_REG_ADDR (0x03020550)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_1_LW_REG_OFFSET (0x00000054)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_1_LW_REG_ADDR (0x03020554)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_1_HW_REG_OFFSET (0x00000058)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_1_HW_REG_ADDR (0x03020558)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_2_LW_REG_OFFSET (0x0000005C)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_2_LW_REG_ADDR (0x0302055C)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_2_HW_REG_OFFSET (0x00000060)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_2_HW_REG_ADDR (0x03020560)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_3_LW_REG_OFFSET (0x00000064)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_3_LW_REG_ADDR (0x03020564)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_3_HW_REG_OFFSET (0x00000068)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_3_HW_REG_ADDR (0x03020568)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_4_LW_REG_OFFSET (0x0000006C)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_4_LW_REG_ADDR (0x0302056C)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_4_HW_REG_OFFSET (0x00000070)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_4_HW_REG_ADDR (0x03020570)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_5_LW_REG_OFFSET (0x00000074)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_5_LW_REG_ADDR (0x03020574)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_5_HW_REG_OFFSET (0x00000078)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_5_HW_REG_ADDR (0x03020578)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_6_LW_REG_OFFSET (0x0000007C)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_6_LW_REG_ADDR (0x0302057C)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_6_HW_REG_OFFSET (0x00000080)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_6_HW_REG_ADDR (0x03020580)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_7_LW_REG_OFFSET (0x00000084)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_7_LW_REG_ADDR (0x03020584)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_7_HW_REG_OFFSET (0x00000088)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_7_HW_REG_ADDR (0x03020588)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_8_LW_REG_OFFSET (0x0000008C)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_8_LW_REG_ADDR (0x0302058C)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_8_HW_REG_OFFSET (0x00000090)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_8_HW_REG_ADDR (0x03020590)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_9_LW_REG_OFFSET (0x00000094)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_9_LW_REG_ADDR (0x03020594)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_9_HW_REG_OFFSET (0x00000098)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_9_HW_REG_ADDR (0x03020598)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_10_LW_REG_OFFSET (0x0000009C)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_10_LW_REG_ADDR (0x0302059C)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_10_HW_REG_OFFSET (0x000000A0)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_10_HW_REG_ADDR (0x030205A0)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_11_LW_REG_OFFSET (0x000000A4)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_11_LW_REG_ADDR (0x030205A4)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_11_HW_REG_OFFSET (0x000000A8)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_11_HW_REG_ADDR (0x030205A8)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_12_LW_REG_OFFSET (0x000000AC)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_12_LW_REG_ADDR (0x030205AC)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_12_HW_REG_OFFSET (0x000000B0)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_12_HW_REG_ADDR (0x030205B0)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_13_LW_REG_OFFSET (0x000000B4)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_13_LW_REG_ADDR (0x030205B4)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_13_HW_REG_OFFSET (0x000000B8)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_13_HW_REG_ADDR (0x030205B8)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_14_LW_REG_OFFSET (0x000000BC)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_14_LW_REG_ADDR (0x030205BC)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_14_HW_REG_OFFSET (0x000000C0)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_14_HW_REG_ADDR (0x030205C0)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_15_LW_REG_OFFSET (0x000000C4)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_15_LW_REG_ADDR (0x030205C4)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_15_HW_REG_OFFSET (0x000000C8)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_15_HW_REG_ADDR (0x030205C8)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_01_K2_REG_OFFSET (0x000000CC)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_01_K2_REG_ADDR (0x030205CC)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_23_K2_REG_OFFSET (0x000000D0)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_23_K2_REG_ADDR (0x030205D0)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_45_K2_REG_OFFSET (0x000000D4)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_45_K2_REG_ADDR (0x030205D4)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_67_K2_REG_OFFSET (0x000000D8)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_67_K2_REG_ADDR (0x030205D8)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_89_K2_REG_OFFSET (0x000000DC)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_89_K2_REG_ADDR (0x030205DC)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_1011_K2_REG_OFFSET (0x000000E0)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_1011_K2_REG_ADDR (0x030205E0)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_1213_K2_REG_OFFSET (0x000000E4)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_1213_K2_REG_ADDR (0x030205E4)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_1415_K2_REG_OFFSET (0x000000E8)
#define TT_NEO_AWM_WRAP_DROOP_0_CONFIG_SETTING_1415_K2_REG_ADDR (0x030205E8)
#define TT_NEO_AWM_WRAP_DROOP_0_PERCENT_DELAY_TH0_REG_OFFSET (0x000000EC)
#define TT_NEO_AWM_WRAP_DROOP_0_PERCENT_DELAY_TH0_REG_ADDR (0x030205EC)
#define TT_NEO_AWM_WRAP_DROOP_0_PERCENT_DELAY_TH1_REG_OFFSET (0x000000F0)
#define TT_NEO_AWM_WRAP_DROOP_0_PERCENT_DELAY_TH1_REG_ADDR (0x030205F0)

//==============================================================================
// Addresses for Address Map: droop_1
//==============================================================================

#define TT_NEO_AWM_WRAP_DROOP_1_REG_MAP_BASE_ADDR (0x03020600)
#define TT_NEO_AWM_WRAP_DROOP_1_REG_MAP_SIZE (0x000000F2)

#define TT_NEO_AWM_WRAP_DROOP_1_ENABLES_REG_OFFSET (0x00000000)
#define TT_NEO_AWM_WRAP_DROOP_1_ENABLES_REG_ADDR (0x03020600)
#define TT_NEO_AWM_WRAP_DROOP_1_SAMPLE_STROBE_REG_OFFSET (0x00000004)
#define TT_NEO_AWM_WRAP_DROOP_1_SAMPLE_STROBE_REG_ADDR (0x03020604)
#define TT_NEO_AWM_WRAP_DROOP_1_TARGET_MONITOR_CODE_REG_OFFSET (0x00000008)
#define TT_NEO_AWM_WRAP_DROOP_1_TARGET_MONITOR_CODE_REG_ADDR (0x03020608)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_REG_OFFSET (0x0000000C)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_REG_ADDR (0x0302060C)
#define TT_NEO_AWM_WRAP_DROOP_1_MEAS_DURATION0_REG_OFFSET (0x00000010)
#define TT_NEO_AWM_WRAP_DROOP_1_MEAS_DURATION0_REG_ADDR (0x03020610)
#define TT_NEO_AWM_WRAP_DROOP_1_MEAS_DURATION1_REG_OFFSET (0x00000014)
#define TT_NEO_AWM_WRAP_DROOP_1_MEAS_DURATION1_REG_ADDR (0x03020614)
#define TT_NEO_AWM_WRAP_DROOP_1_LONG_TERM_MAX_CODE_REG_OFFSET (0x00000018)
#define TT_NEO_AWM_WRAP_DROOP_1_LONG_TERM_MAX_CODE_REG_ADDR (0x03020618)
#define TT_NEO_AWM_WRAP_DROOP_1_LONG_TERM_MIN_CODE_REG_OFFSET (0x0000001C)
#define TT_NEO_AWM_WRAP_DROOP_1_LONG_TERM_MIN_CODE_REG_ADDR (0x0302061C)
#define TT_NEO_AWM_WRAP_DROOP_1_EXT_DROOP_DUR0_REG_OFFSET (0x00000020)
#define TT_NEO_AWM_WRAP_DROOP_1_EXT_DROOP_DUR0_REG_ADDR (0x03020620)
#define TT_NEO_AWM_WRAP_DROOP_1_EXT_DROOP_DUR1_REG_OFFSET (0x00000024)
#define TT_NEO_AWM_WRAP_DROOP_1_EXT_DROOP_DUR1_REG_ADDR (0x03020624)
#define TT_NEO_AWM_WRAP_DROOP_1_EXT_DROOP_DUR2_REG_OFFSET (0x00000028)
#define TT_NEO_AWM_WRAP_DROOP_1_EXT_DROOP_DUR2_REG_ADDR (0x03020628)
#define TT_NEO_AWM_WRAP_DROOP_1_EXT_DROOP_DUR3_REG_OFFSET (0x0000002C)
#define TT_NEO_AWM_WRAP_DROOP_1_EXT_DROOP_DUR3_REG_ADDR (0x0302062C)
#define TT_NEO_AWM_WRAP_DROOP_1_EXT_DROOP_TRAN_01_REG_OFFSET (0x00000030)
#define TT_NEO_AWM_WRAP_DROOP_1_EXT_DROOP_TRAN_01_REG_ADDR (0x03020630)
#define TT_NEO_AWM_WRAP_DROOP_1_EXT_DROOP_TRAN_23_REG_OFFSET (0x00000034)
#define TT_NEO_AWM_WRAP_DROOP_1_EXT_DROOP_TRAN_23_REG_ADDR (0x03020634)
#define TT_NEO_AWM_WRAP_DROOP_1_FORCE_REG_OFFSET (0x00000038)
#define TT_NEO_AWM_WRAP_DROOP_1_FORCE_REG_ADDR (0x03020638)
#define TT_NEO_AWM_WRAP_DROOP_1_SAMPLED_AVG_MONITOR_REG_OFFSET (0x0000003C)
#define TT_NEO_AWM_WRAP_DROOP_1_SAMPLED_AVG_MONITOR_REG_ADDR (0x0302063C)
#define TT_NEO_AWM_WRAP_DROOP_1_SAMPLED_DROOP_REG_OFFSET (0x00000040)
#define TT_NEO_AWM_WRAP_DROOP_1_SAMPLED_DROOP_REG_ADDR (0x03020640)
#define TT_NEO_AWM_WRAP_DROOP_1_SAMPLED_MONITOR_REG_OFFSET (0x00000044)
#define TT_NEO_AWM_WRAP_DROOP_1_SAMPLED_MONITOR_REG_ADDR (0x03020644)
#define TT_NEO_AWM_WRAP_DROOP_1_SAMPLED_DELAY_REG_OFFSET (0x00000048)
#define TT_NEO_AWM_WRAP_DROOP_1_SAMPLED_DELAY_REG_ADDR (0x03020648)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_0_LW_REG_OFFSET (0x0000004C)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_0_LW_REG_ADDR (0x0302064C)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_0_HW_REG_OFFSET (0x00000050)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_0_HW_REG_ADDR (0x03020650)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_1_LW_REG_OFFSET (0x00000054)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_1_LW_REG_ADDR (0x03020654)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_1_HW_REG_OFFSET (0x00000058)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_1_HW_REG_ADDR (0x03020658)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_2_LW_REG_OFFSET (0x0000005C)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_2_LW_REG_ADDR (0x0302065C)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_2_HW_REG_OFFSET (0x00000060)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_2_HW_REG_ADDR (0x03020660)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_3_LW_REG_OFFSET (0x00000064)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_3_LW_REG_ADDR (0x03020664)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_3_HW_REG_OFFSET (0x00000068)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_3_HW_REG_ADDR (0x03020668)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_4_LW_REG_OFFSET (0x0000006C)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_4_LW_REG_ADDR (0x0302066C)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_4_HW_REG_OFFSET (0x00000070)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_4_HW_REG_ADDR (0x03020670)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_5_LW_REG_OFFSET (0x00000074)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_5_LW_REG_ADDR (0x03020674)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_5_HW_REG_OFFSET (0x00000078)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_5_HW_REG_ADDR (0x03020678)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_6_LW_REG_OFFSET (0x0000007C)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_6_LW_REG_ADDR (0x0302067C)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_6_HW_REG_OFFSET (0x00000080)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_6_HW_REG_ADDR (0x03020680)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_7_LW_REG_OFFSET (0x00000084)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_7_LW_REG_ADDR (0x03020684)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_7_HW_REG_OFFSET (0x00000088)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_7_HW_REG_ADDR (0x03020688)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_8_LW_REG_OFFSET (0x0000008C)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_8_LW_REG_ADDR (0x0302068C)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_8_HW_REG_OFFSET (0x00000090)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_8_HW_REG_ADDR (0x03020690)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_9_LW_REG_OFFSET (0x00000094)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_9_LW_REG_ADDR (0x03020694)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_9_HW_REG_OFFSET (0x00000098)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_9_HW_REG_ADDR (0x03020698)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_10_LW_REG_OFFSET (0x0000009C)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_10_LW_REG_ADDR (0x0302069C)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_10_HW_REG_OFFSET (0x000000A0)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_10_HW_REG_ADDR (0x030206A0)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_11_LW_REG_OFFSET (0x000000A4)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_11_LW_REG_ADDR (0x030206A4)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_11_HW_REG_OFFSET (0x000000A8)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_11_HW_REG_ADDR (0x030206A8)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_12_LW_REG_OFFSET (0x000000AC)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_12_LW_REG_ADDR (0x030206AC)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_12_HW_REG_OFFSET (0x000000B0)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_12_HW_REG_ADDR (0x030206B0)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_13_LW_REG_OFFSET (0x000000B4)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_13_LW_REG_ADDR (0x030206B4)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_13_HW_REG_OFFSET (0x000000B8)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_13_HW_REG_ADDR (0x030206B8)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_14_LW_REG_OFFSET (0x000000BC)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_14_LW_REG_ADDR (0x030206BC)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_14_HW_REG_OFFSET (0x000000C0)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_14_HW_REG_ADDR (0x030206C0)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_15_LW_REG_OFFSET (0x000000C4)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_15_LW_REG_ADDR (0x030206C4)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_15_HW_REG_OFFSET (0x000000C8)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_15_HW_REG_ADDR (0x030206C8)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_01_K2_REG_OFFSET (0x000000CC)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_01_K2_REG_ADDR (0x030206CC)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_23_K2_REG_OFFSET (0x000000D0)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_23_K2_REG_ADDR (0x030206D0)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_45_K2_REG_OFFSET (0x000000D4)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_45_K2_REG_ADDR (0x030206D4)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_67_K2_REG_OFFSET (0x000000D8)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_67_K2_REG_ADDR (0x030206D8)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_89_K2_REG_OFFSET (0x000000DC)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_89_K2_REG_ADDR (0x030206DC)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_1011_K2_REG_OFFSET (0x000000E0)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_1011_K2_REG_ADDR (0x030206E0)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_1213_K2_REG_OFFSET (0x000000E4)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_1213_K2_REG_ADDR (0x030206E4)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_1415_K2_REG_OFFSET (0x000000E8)
#define TT_NEO_AWM_WRAP_DROOP_1_CONFIG_SETTING_1415_K2_REG_ADDR (0x030206E8)
#define TT_NEO_AWM_WRAP_DROOP_1_PERCENT_DELAY_TH0_REG_OFFSET (0x000000EC)
#define TT_NEO_AWM_WRAP_DROOP_1_PERCENT_DELAY_TH0_REG_ADDR (0x030206EC)
#define TT_NEO_AWM_WRAP_DROOP_1_PERCENT_DELAY_TH1_REG_OFFSET (0x000000F0)
#define TT_NEO_AWM_WRAP_DROOP_1_PERCENT_DELAY_TH1_REG_ADDR (0x030206F0)

//==============================================================================
// Addresses for Address Map: droop_2
//==============================================================================

#define TT_NEO_AWM_WRAP_DROOP_2_REG_MAP_BASE_ADDR (0x03020700)
#define TT_NEO_AWM_WRAP_DROOP_2_REG_MAP_SIZE (0x000000F2)

#define TT_NEO_AWM_WRAP_DROOP_2_ENABLES_REG_OFFSET (0x00000000)
#define TT_NEO_AWM_WRAP_DROOP_2_ENABLES_REG_ADDR (0x03020700)
#define TT_NEO_AWM_WRAP_DROOP_2_SAMPLE_STROBE_REG_OFFSET (0x00000004)
#define TT_NEO_AWM_WRAP_DROOP_2_SAMPLE_STROBE_REG_ADDR (0x03020704)
#define TT_NEO_AWM_WRAP_DROOP_2_TARGET_MONITOR_CODE_REG_OFFSET (0x00000008)
#define TT_NEO_AWM_WRAP_DROOP_2_TARGET_MONITOR_CODE_REG_ADDR (0x03020708)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_REG_OFFSET (0x0000000C)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_REG_ADDR (0x0302070C)
#define TT_NEO_AWM_WRAP_DROOP_2_MEAS_DURATION0_REG_OFFSET (0x00000010)
#define TT_NEO_AWM_WRAP_DROOP_2_MEAS_DURATION0_REG_ADDR (0x03020710)
#define TT_NEO_AWM_WRAP_DROOP_2_MEAS_DURATION1_REG_OFFSET (0x00000014)
#define TT_NEO_AWM_WRAP_DROOP_2_MEAS_DURATION1_REG_ADDR (0x03020714)
#define TT_NEO_AWM_WRAP_DROOP_2_LONG_TERM_MAX_CODE_REG_OFFSET (0x00000018)
#define TT_NEO_AWM_WRAP_DROOP_2_LONG_TERM_MAX_CODE_REG_ADDR (0x03020718)
#define TT_NEO_AWM_WRAP_DROOP_2_LONG_TERM_MIN_CODE_REG_OFFSET (0x0000001C)
#define TT_NEO_AWM_WRAP_DROOP_2_LONG_TERM_MIN_CODE_REG_ADDR (0x0302071C)
#define TT_NEO_AWM_WRAP_DROOP_2_EXT_DROOP_DUR0_REG_OFFSET (0x00000020)
#define TT_NEO_AWM_WRAP_DROOP_2_EXT_DROOP_DUR0_REG_ADDR (0x03020720)
#define TT_NEO_AWM_WRAP_DROOP_2_EXT_DROOP_DUR1_REG_OFFSET (0x00000024)
#define TT_NEO_AWM_WRAP_DROOP_2_EXT_DROOP_DUR1_REG_ADDR (0x03020724)
#define TT_NEO_AWM_WRAP_DROOP_2_EXT_DROOP_DUR2_REG_OFFSET (0x00000028)
#define TT_NEO_AWM_WRAP_DROOP_2_EXT_DROOP_DUR2_REG_ADDR (0x03020728)
#define TT_NEO_AWM_WRAP_DROOP_2_EXT_DROOP_DUR3_REG_OFFSET (0x0000002C)
#define TT_NEO_AWM_WRAP_DROOP_2_EXT_DROOP_DUR3_REG_ADDR (0x0302072C)
#define TT_NEO_AWM_WRAP_DROOP_2_EXT_DROOP_TRAN_01_REG_OFFSET (0x00000030)
#define TT_NEO_AWM_WRAP_DROOP_2_EXT_DROOP_TRAN_01_REG_ADDR (0x03020730)
#define TT_NEO_AWM_WRAP_DROOP_2_EXT_DROOP_TRAN_23_REG_OFFSET (0x00000034)
#define TT_NEO_AWM_WRAP_DROOP_2_EXT_DROOP_TRAN_23_REG_ADDR (0x03020734)
#define TT_NEO_AWM_WRAP_DROOP_2_FORCE_REG_OFFSET (0x00000038)
#define TT_NEO_AWM_WRAP_DROOP_2_FORCE_REG_ADDR (0x03020738)
#define TT_NEO_AWM_WRAP_DROOP_2_SAMPLED_AVG_MONITOR_REG_OFFSET (0x0000003C)
#define TT_NEO_AWM_WRAP_DROOP_2_SAMPLED_AVG_MONITOR_REG_ADDR (0x0302073C)
#define TT_NEO_AWM_WRAP_DROOP_2_SAMPLED_DROOP_REG_OFFSET (0x00000040)
#define TT_NEO_AWM_WRAP_DROOP_2_SAMPLED_DROOP_REG_ADDR (0x03020740)
#define TT_NEO_AWM_WRAP_DROOP_2_SAMPLED_MONITOR_REG_OFFSET (0x00000044)
#define TT_NEO_AWM_WRAP_DROOP_2_SAMPLED_MONITOR_REG_ADDR (0x03020744)
#define TT_NEO_AWM_WRAP_DROOP_2_SAMPLED_DELAY_REG_OFFSET (0x00000048)
#define TT_NEO_AWM_WRAP_DROOP_2_SAMPLED_DELAY_REG_ADDR (0x03020748)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_0_LW_REG_OFFSET (0x0000004C)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_0_LW_REG_ADDR (0x0302074C)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_0_HW_REG_OFFSET (0x00000050)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_0_HW_REG_ADDR (0x03020750)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_1_LW_REG_OFFSET (0x00000054)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_1_LW_REG_ADDR (0x03020754)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_1_HW_REG_OFFSET (0x00000058)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_1_HW_REG_ADDR (0x03020758)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_2_LW_REG_OFFSET (0x0000005C)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_2_LW_REG_ADDR (0x0302075C)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_2_HW_REG_OFFSET (0x00000060)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_2_HW_REG_ADDR (0x03020760)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_3_LW_REG_OFFSET (0x00000064)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_3_LW_REG_ADDR (0x03020764)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_3_HW_REG_OFFSET (0x00000068)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_3_HW_REG_ADDR (0x03020768)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_4_LW_REG_OFFSET (0x0000006C)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_4_LW_REG_ADDR (0x0302076C)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_4_HW_REG_OFFSET (0x00000070)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_4_HW_REG_ADDR (0x03020770)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_5_LW_REG_OFFSET (0x00000074)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_5_LW_REG_ADDR (0x03020774)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_5_HW_REG_OFFSET (0x00000078)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_5_HW_REG_ADDR (0x03020778)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_6_LW_REG_OFFSET (0x0000007C)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_6_LW_REG_ADDR (0x0302077C)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_6_HW_REG_OFFSET (0x00000080)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_6_HW_REG_ADDR (0x03020780)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_7_LW_REG_OFFSET (0x00000084)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_7_LW_REG_ADDR (0x03020784)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_7_HW_REG_OFFSET (0x00000088)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_7_HW_REG_ADDR (0x03020788)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_8_LW_REG_OFFSET (0x0000008C)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_8_LW_REG_ADDR (0x0302078C)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_8_HW_REG_OFFSET (0x00000090)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_8_HW_REG_ADDR (0x03020790)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_9_LW_REG_OFFSET (0x00000094)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_9_LW_REG_ADDR (0x03020794)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_9_HW_REG_OFFSET (0x00000098)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_9_HW_REG_ADDR (0x03020798)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_10_LW_REG_OFFSET (0x0000009C)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_10_LW_REG_ADDR (0x0302079C)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_10_HW_REG_OFFSET (0x000000A0)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_10_HW_REG_ADDR (0x030207A0)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_11_LW_REG_OFFSET (0x000000A4)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_11_LW_REG_ADDR (0x030207A4)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_11_HW_REG_OFFSET (0x000000A8)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_11_HW_REG_ADDR (0x030207A8)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_12_LW_REG_OFFSET (0x000000AC)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_12_LW_REG_ADDR (0x030207AC)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_12_HW_REG_OFFSET (0x000000B0)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_12_HW_REG_ADDR (0x030207B0)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_13_LW_REG_OFFSET (0x000000B4)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_13_LW_REG_ADDR (0x030207B4)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_13_HW_REG_OFFSET (0x000000B8)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_13_HW_REG_ADDR (0x030207B8)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_14_LW_REG_OFFSET (0x000000BC)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_14_LW_REG_ADDR (0x030207BC)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_14_HW_REG_OFFSET (0x000000C0)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_14_HW_REG_ADDR (0x030207C0)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_15_LW_REG_OFFSET (0x000000C4)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_15_LW_REG_ADDR (0x030207C4)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_15_HW_REG_OFFSET (0x000000C8)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_15_HW_REG_ADDR (0x030207C8)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_01_K2_REG_OFFSET (0x000000CC)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_01_K2_REG_ADDR (0x030207CC)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_23_K2_REG_OFFSET (0x000000D0)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_23_K2_REG_ADDR (0x030207D0)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_45_K2_REG_OFFSET (0x000000D4)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_45_K2_REG_ADDR (0x030207D4)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_67_K2_REG_OFFSET (0x000000D8)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_67_K2_REG_ADDR (0x030207D8)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_89_K2_REG_OFFSET (0x000000DC)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_89_K2_REG_ADDR (0x030207DC)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_1011_K2_REG_OFFSET (0x000000E0)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_1011_K2_REG_ADDR (0x030207E0)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_1213_K2_REG_OFFSET (0x000000E4)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_1213_K2_REG_ADDR (0x030207E4)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_1415_K2_REG_OFFSET (0x000000E8)
#define TT_NEO_AWM_WRAP_DROOP_2_CONFIG_SETTING_1415_K2_REG_ADDR (0x030207E8)
#define TT_NEO_AWM_WRAP_DROOP_2_PERCENT_DELAY_TH0_REG_OFFSET (0x000000EC)
#define TT_NEO_AWM_WRAP_DROOP_2_PERCENT_DELAY_TH0_REG_ADDR (0x030207EC)
#define TT_NEO_AWM_WRAP_DROOP_2_PERCENT_DELAY_TH1_REG_OFFSET (0x000000F0)
#define TT_NEO_AWM_WRAP_DROOP_2_PERCENT_DELAY_TH1_REG_ADDR (0x030207F0)

//==============================================================================
// Addresses for Address Map: droop_3
//==============================================================================

#define TT_NEO_AWM_WRAP_DROOP_3_REG_MAP_BASE_ADDR (0x03020800)
#define TT_NEO_AWM_WRAP_DROOP_3_REG_MAP_SIZE (0x000000F2)

#define TT_NEO_AWM_WRAP_DROOP_3_ENABLES_REG_OFFSET (0x00000000)
#define TT_NEO_AWM_WRAP_DROOP_3_ENABLES_REG_ADDR (0x03020800)
#define TT_NEO_AWM_WRAP_DROOP_3_SAMPLE_STROBE_REG_OFFSET (0x00000004)
#define TT_NEO_AWM_WRAP_DROOP_3_SAMPLE_STROBE_REG_ADDR (0x03020804)
#define TT_NEO_AWM_WRAP_DROOP_3_TARGET_MONITOR_CODE_REG_OFFSET (0x00000008)
#define TT_NEO_AWM_WRAP_DROOP_3_TARGET_MONITOR_CODE_REG_ADDR (0x03020808)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_REG_OFFSET (0x0000000C)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_REG_ADDR (0x0302080C)
#define TT_NEO_AWM_WRAP_DROOP_3_MEAS_DURATION0_REG_OFFSET (0x00000010)
#define TT_NEO_AWM_WRAP_DROOP_3_MEAS_DURATION0_REG_ADDR (0x03020810)
#define TT_NEO_AWM_WRAP_DROOP_3_MEAS_DURATION1_REG_OFFSET (0x00000014)
#define TT_NEO_AWM_WRAP_DROOP_3_MEAS_DURATION1_REG_ADDR (0x03020814)
#define TT_NEO_AWM_WRAP_DROOP_3_LONG_TERM_MAX_CODE_REG_OFFSET (0x00000018)
#define TT_NEO_AWM_WRAP_DROOP_3_LONG_TERM_MAX_CODE_REG_ADDR (0x03020818)
#define TT_NEO_AWM_WRAP_DROOP_3_LONG_TERM_MIN_CODE_REG_OFFSET (0x0000001C)
#define TT_NEO_AWM_WRAP_DROOP_3_LONG_TERM_MIN_CODE_REG_ADDR (0x0302081C)
#define TT_NEO_AWM_WRAP_DROOP_3_EXT_DROOP_DUR0_REG_OFFSET (0x00000020)
#define TT_NEO_AWM_WRAP_DROOP_3_EXT_DROOP_DUR0_REG_ADDR (0x03020820)
#define TT_NEO_AWM_WRAP_DROOP_3_EXT_DROOP_DUR1_REG_OFFSET (0x00000024)
#define TT_NEO_AWM_WRAP_DROOP_3_EXT_DROOP_DUR1_REG_ADDR (0x03020824)
#define TT_NEO_AWM_WRAP_DROOP_3_EXT_DROOP_DUR2_REG_OFFSET (0x00000028)
#define TT_NEO_AWM_WRAP_DROOP_3_EXT_DROOP_DUR2_REG_ADDR (0x03020828)
#define TT_NEO_AWM_WRAP_DROOP_3_EXT_DROOP_DUR3_REG_OFFSET (0x0000002C)
#define TT_NEO_AWM_WRAP_DROOP_3_EXT_DROOP_DUR3_REG_ADDR (0x0302082C)
#define TT_NEO_AWM_WRAP_DROOP_3_EXT_DROOP_TRAN_01_REG_OFFSET (0x00000030)
#define TT_NEO_AWM_WRAP_DROOP_3_EXT_DROOP_TRAN_01_REG_ADDR (0x03020830)
#define TT_NEO_AWM_WRAP_DROOP_3_EXT_DROOP_TRAN_23_REG_OFFSET (0x00000034)
#define TT_NEO_AWM_WRAP_DROOP_3_EXT_DROOP_TRAN_23_REG_ADDR (0x03020834)
#define TT_NEO_AWM_WRAP_DROOP_3_FORCE_REG_OFFSET (0x00000038)
#define TT_NEO_AWM_WRAP_DROOP_3_FORCE_REG_ADDR (0x03020838)
#define TT_NEO_AWM_WRAP_DROOP_3_SAMPLED_AVG_MONITOR_REG_OFFSET (0x0000003C)
#define TT_NEO_AWM_WRAP_DROOP_3_SAMPLED_AVG_MONITOR_REG_ADDR (0x0302083C)
#define TT_NEO_AWM_WRAP_DROOP_3_SAMPLED_DROOP_REG_OFFSET (0x00000040)
#define TT_NEO_AWM_WRAP_DROOP_3_SAMPLED_DROOP_REG_ADDR (0x03020840)
#define TT_NEO_AWM_WRAP_DROOP_3_SAMPLED_MONITOR_REG_OFFSET (0x00000044)
#define TT_NEO_AWM_WRAP_DROOP_3_SAMPLED_MONITOR_REG_ADDR (0x03020844)
#define TT_NEO_AWM_WRAP_DROOP_3_SAMPLED_DELAY_REG_OFFSET (0x00000048)
#define TT_NEO_AWM_WRAP_DROOP_3_SAMPLED_DELAY_REG_ADDR (0x03020848)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_0_LW_REG_OFFSET (0x0000004C)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_0_LW_REG_ADDR (0x0302084C)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_0_HW_REG_OFFSET (0x00000050)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_0_HW_REG_ADDR (0x03020850)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_1_LW_REG_OFFSET (0x00000054)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_1_LW_REG_ADDR (0x03020854)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_1_HW_REG_OFFSET (0x00000058)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_1_HW_REG_ADDR (0x03020858)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_2_LW_REG_OFFSET (0x0000005C)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_2_LW_REG_ADDR (0x0302085C)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_2_HW_REG_OFFSET (0x00000060)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_2_HW_REG_ADDR (0x03020860)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_3_LW_REG_OFFSET (0x00000064)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_3_LW_REG_ADDR (0x03020864)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_3_HW_REG_OFFSET (0x00000068)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_3_HW_REG_ADDR (0x03020868)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_4_LW_REG_OFFSET (0x0000006C)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_4_LW_REG_ADDR (0x0302086C)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_4_HW_REG_OFFSET (0x00000070)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_4_HW_REG_ADDR (0x03020870)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_5_LW_REG_OFFSET (0x00000074)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_5_LW_REG_ADDR (0x03020874)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_5_HW_REG_OFFSET (0x00000078)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_5_HW_REG_ADDR (0x03020878)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_6_LW_REG_OFFSET (0x0000007C)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_6_LW_REG_ADDR (0x0302087C)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_6_HW_REG_OFFSET (0x00000080)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_6_HW_REG_ADDR (0x03020880)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_7_LW_REG_OFFSET (0x00000084)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_7_LW_REG_ADDR (0x03020884)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_7_HW_REG_OFFSET (0x00000088)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_7_HW_REG_ADDR (0x03020888)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_8_LW_REG_OFFSET (0x0000008C)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_8_LW_REG_ADDR (0x0302088C)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_8_HW_REG_OFFSET (0x00000090)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_8_HW_REG_ADDR (0x03020890)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_9_LW_REG_OFFSET (0x00000094)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_9_LW_REG_ADDR (0x03020894)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_9_HW_REG_OFFSET (0x00000098)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_9_HW_REG_ADDR (0x03020898)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_10_LW_REG_OFFSET (0x0000009C)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_10_LW_REG_ADDR (0x0302089C)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_10_HW_REG_OFFSET (0x000000A0)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_10_HW_REG_ADDR (0x030208A0)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_11_LW_REG_OFFSET (0x000000A4)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_11_LW_REG_ADDR (0x030208A4)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_11_HW_REG_OFFSET (0x000000A8)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_11_HW_REG_ADDR (0x030208A8)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_12_LW_REG_OFFSET (0x000000AC)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_12_LW_REG_ADDR (0x030208AC)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_12_HW_REG_OFFSET (0x000000B0)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_12_HW_REG_ADDR (0x030208B0)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_13_LW_REG_OFFSET (0x000000B4)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_13_LW_REG_ADDR (0x030208B4)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_13_HW_REG_OFFSET (0x000000B8)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_13_HW_REG_ADDR (0x030208B8)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_14_LW_REG_OFFSET (0x000000BC)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_14_LW_REG_ADDR (0x030208BC)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_14_HW_REG_OFFSET (0x000000C0)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_14_HW_REG_ADDR (0x030208C0)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_15_LW_REG_OFFSET (0x000000C4)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_15_LW_REG_ADDR (0x030208C4)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_15_HW_REG_OFFSET (0x000000C8)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_15_HW_REG_ADDR (0x030208C8)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_01_K2_REG_OFFSET (0x000000CC)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_01_K2_REG_ADDR (0x030208CC)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_23_K2_REG_OFFSET (0x000000D0)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_23_K2_REG_ADDR (0x030208D0)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_45_K2_REG_OFFSET (0x000000D4)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_45_K2_REG_ADDR (0x030208D4)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_67_K2_REG_OFFSET (0x000000D8)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_67_K2_REG_ADDR (0x030208D8)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_89_K2_REG_OFFSET (0x000000DC)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_89_K2_REG_ADDR (0x030208DC)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_1011_K2_REG_OFFSET (0x000000E0)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_1011_K2_REG_ADDR (0x030208E0)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_1213_K2_REG_OFFSET (0x000000E4)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_1213_K2_REG_ADDR (0x030208E4)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_1415_K2_REG_OFFSET (0x000000E8)
#define TT_NEO_AWM_WRAP_DROOP_3_CONFIG_SETTING_1415_K2_REG_ADDR (0x030208E8)
#define TT_NEO_AWM_WRAP_DROOP_3_PERCENT_DELAY_TH0_REG_OFFSET (0x000000EC)
#define TT_NEO_AWM_WRAP_DROOP_3_PERCENT_DELAY_TH0_REG_ADDR (0x030208EC)
#define TT_NEO_AWM_WRAP_DROOP_3_PERCENT_DELAY_TH1_REG_OFFSET (0x000000F0)
#define TT_NEO_AWM_WRAP_DROOP_3_PERCENT_DELAY_TH1_REG_ADDR (0x030208F0)

//==============================================================================
// Addresses for Address Map: tt_pll_pvt
//==============================================================================

#define TT_NEO_AWM_WRAP_TT_PLL_PVT_REG_MAP_BASE_ADDR (0x03020900)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_REG_MAP_SIZE (0x000000BC)

#define TT_NEO_AWM_WRAP_TT_PLL_PVT_PROGRAMMABLE_THRESHOLD_REG_OFFSET (0x00000000)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_PROGRAMMABLE_THRESHOLD_REG_ADDR (0x03020900)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_DEBUG_TEMP_VAL_REG_OFFSET (0x00000004)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_DEBUG_TEMP_VAL_REG_ADDR (0x03020904)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_DELTA_THRESHOLD_PLUS_REG_OFFSET (0x00000008)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_DELTA_THRESHOLD_PLUS_REG_ADDR (0x03020908)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_DELTA_THRESHOLD_MNUS_REG_OFFSET (0x0000000C)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_DELTA_THRESHOLD_MNUS_REG_ADDR (0x0302090C)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_FREQ_SEL_STEP_SIZE_REG_OFFSET (0x00000010)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_FREQ_SEL_STEP_SIZE_REG_ADDR (0x03020910)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_THERMAL_CTRL_LOOP_CFG_REG_OFFSET (0x00000014)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_THERMAL_CTRL_LOOP_CFG_REG_ADDR (0x03020914)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_RESET_P_STATE_REG_OFFSET (0x00000018)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_RESET_P_STATE_REG_ADDR (0x03020918)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_HYSTERESIS_COUNTER_REG_OFFSET (0x0000001C)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_HYSTERESIS_COUNTER_REG_ADDR (0x0302091C)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_INCREASE_FREQ_EVENT_COUNT_REG_OFFSET (0x00000020)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_INCREASE_FREQ_EVENT_COUNT_REG_ADDR (0x03020920)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_REDUCE_FREQ_EVENT_COUNT_REG_OFFSET (0x00000024)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_REDUCE_FREQ_EVENT_COUNT_REG_ADDR (0x03020924)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_THERMAL_CTRL_STATUS_REG_OFFSET (0x00000028)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_THERMAL_CTRL_STATUS_REG_ADDR (0x03020928)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_LOOKUP_FCW_INT_FREQ0_REG_OFFSET (0x0000002C)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_LOOKUP_FCW_INT_FREQ0_REG_ADDR (0x0302092C)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_LOOKUP_FCW_INT_FREQ1_REG_OFFSET (0x00000030)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_LOOKUP_FCW_INT_FREQ1_REG_ADDR (0x03020930)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_LOOKUP_FCW_INT_FREQ2_REG_OFFSET (0x00000034)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_LOOKUP_FCW_INT_FREQ2_REG_ADDR (0x03020934)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_LOOKUP_FCW_INT_FREQ3_REG_OFFSET (0x00000038)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_LOOKUP_FCW_INT_FREQ3_REG_ADDR (0x03020938)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_LOOKUP_FCW_INT_FREQ4_REG_OFFSET (0x0000003C)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_LOOKUP_FCW_INT_FREQ4_REG_ADDR (0x0302093C)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_LOOKUP_FCW_INT_FREQ5_REG_OFFSET (0x00000040)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_LOOKUP_FCW_INT_FREQ5_REG_ADDR (0x03020940)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_LOOKUP_FCW_INT_FREQ6_REG_OFFSET (0x00000044)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_LOOKUP_FCW_INT_FREQ6_REG_ADDR (0x03020944)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_LOOKUP_FCW_INT_FREQ7_REG_OFFSET (0x00000048)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_LOOKUP_FCW_INT_FREQ7_REG_ADDR (0x03020948)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_LOOKUP_FCW_INT_FREQ8_REG_OFFSET (0x0000004C)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_LOOKUP_FCW_INT_FREQ8_REG_ADDR (0x0302094C)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_LOOKUP_FCW_INT_FREQ9_REG_OFFSET (0x00000050)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_LOOKUP_FCW_INT_FREQ9_REG_ADDR (0x03020950)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_LOOKUP_FCW_INT_FREQ10_REG_OFFSET (0x00000054)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_LOOKUP_FCW_INT_FREQ10_REG_ADDR (0x03020954)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_LOOKUP_FCW_INT_FREQ11_REG_OFFSET (0x00000058)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_LOOKUP_FCW_INT_FREQ11_REG_ADDR (0x03020958)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_LOOKUP_FCW_INT_FREQ12_REG_OFFSET (0x0000005C)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_LOOKUP_FCW_INT_FREQ12_REG_ADDR (0x0302095C)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_LOOKUP_FCW_INT_FREQ13_REG_OFFSET (0x00000060)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_LOOKUP_FCW_INT_FREQ13_REG_ADDR (0x03020960)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_LOOKUP_FCW_INT_FREQ14_REG_OFFSET (0x00000064)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_LOOKUP_FCW_INT_FREQ14_REG_ADDR (0x03020964)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_LOOKUP_FCW_INT_FREQ15_REG_OFFSET (0x00000068)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_LOOKUP_FCW_INT_FREQ15_REG_ADDR (0x03020968)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_PROMISE_SENSOR_CTRL_REG_OFFSET (0x0000006C)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_PROMISE_SENSOR_CTRL_REG_ADDR (0x0302096C)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_THERMAL_THRESHOLDS_REG_OFFSET (0x00000070)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_THERMAL_THRESHOLDS_REG_ADDR (0x03020970)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_THERMAL_THRESHOLDS_REACHED_REG_OFFSET (0x00000074)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_THERMAL_THRESHOLDS_REACHED_REG_ADDR (0x03020974)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_POLL_TEMP_REG_OFFSET (0x00000078)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_POLL_TEMP_REG_ADDR (0x03020978)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_CLOCK_COUNTER_CTRL_REG_OFFSET (0x0000007C)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_CLOCK_COUNTER_CTRL_REG_ADDR (0x0302097C)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_REF_CLK_COUNT_PERIOD_LO_REG_OFFSET (0x00000080)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_REF_CLK_COUNT_PERIOD_LO_REG_ADDR (0x03020980)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_REF_CLK_COUNT_PERIOD_HI_REG_OFFSET (0x00000084)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_REF_CLK_COUNT_PERIOD_HI_REG_ADDR (0x03020984)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_CLOCK_COUNTER_STATUS_REG_OFFSET (0x00000088)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_CLOCK_COUNTER_STATUS_REG_ADDR (0x03020988)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_AWM_0_CLOCK_0_COUNT_LO_REG_OFFSET (0x0000008C)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_AWM_0_CLOCK_0_COUNT_LO_REG_ADDR (0x0302098C)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_AWM_0_CLOCK_0_COUNT_HI_REG_OFFSET (0x00000090)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_AWM_0_CLOCK_0_COUNT_HI_REG_ADDR (0x03020990)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_AWM_0_CLOCK_2_COUNT_LO_REG_OFFSET (0x00000094)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_AWM_0_CLOCK_2_COUNT_LO_REG_ADDR (0x03020994)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_AWM_0_CLOCK_2_COUNT_HI_REG_OFFSET (0x00000098)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_AWM_0_CLOCK_2_COUNT_HI_REG_ADDR (0x03020998)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_PM_0_COUNT_LO_REG_OFFSET (0x0000009C)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_PM_0_COUNT_LO_REG_ADDR (0x0302099C)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_PM_0_COUNT_HI_REG_OFFSET (0x000000A0)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_PM_0_COUNT_HI_REG_ADDR (0x030209A0)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_PM_1_COUNT_LO_REG_OFFSET (0x000000A4)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_PM_1_COUNT_LO_REG_ADDR (0x030209A4)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_PM_1_COUNT_HI_REG_OFFSET (0x000000A8)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_PM_1_COUNT_HI_REG_ADDR (0x030209A8)

//==============================================================================
// Register File: pll_pvt_clk_observe
//==============================================================================

#define TT_NEO_AWM_WRAP_TT_PLL_PVT_PLL_PVT_CLK_OBSERVE_REG_FILE_BASE_ADDR (0x030209B0)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_PLL_PVT_CLK_OBSERVE_REG_FILE_SIZE (0x0000000C)

#define TT_NEO_AWM_WRAP_TT_PLL_PVT_PLL_PVT_CLK_OBSERVE_CLK_CTR_CONFIG_REG_OFFSET (0x00000000)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_PLL_PVT_CLK_OBSERVE_CLK_CTR_CONFIG_REG_ADDR (0x030209B0)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_PLL_PVT_CLK_OBSERVE_CLK_CTR_OUT_REG_OFFSET (0x00000004)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_PLL_PVT_CLK_OBSERVE_CLK_CTR_OUT_REG_ADDR (0x030209B4)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_PLL_PVT_CLK_OBSERVE_CLK_CTR_FUNCTIONAL_REG_OFFSET (0x00000008)
#define TT_NEO_AWM_WRAP_TT_PLL_PVT_PLL_PVT_CLK_OBSERVE_CLK_CTR_FUNCTIONAL_REG_ADDR (0x030209B8)

//==============================================================================
// Addresses for Address Map: temp_sensor
//==============================================================================

#define TT_NEO_AWM_WRAP_TEMP_SENSOR_REG_MAP_BASE_ADDR (0x03020A00)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_REG_MAP_SIZE (0x000000C0)

#define TT_NEO_AWM_WRAP_TEMP_SENSOR_TEMP_SENSOR_CTRL_REG_OFFSET (0x00000000)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_TEMP_SENSOR_CTRL_REG_ADDR (0x03020A00)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_BYPASS_ID_LO_REG_OFFSET (0x00000004)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_BYPASS_ID_LO_REG_ADDR (0x03020A04)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_BYPASS_ID_HI_REG_OFFSET (0x00000008)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_BYPASS_ID_HI_REG_ADDR (0x03020A08)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_TEMP_SENSOR_CFG_0_REG_OFFSET (0x0000000C)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_TEMP_SENSOR_CFG_0_REG_ADDR (0x03020A0C)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_TEMP_SENSOR_CFG_1_REG_OFFSET (0x00000010)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_TEMP_SENSOR_CFG_1_REG_ADDR (0x03020A10)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_TEMP_COEFF_B_REG_OFFSET (0x00000014)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_TEMP_COEFF_B_REG_ADDR (0x03020A14)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_TEMP_COEFF_C_REG_OFFSET (0x00000018)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_TEMP_COEFF_C_REG_ADDR (0x03020A18)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_DAC_GAIN_REG_OFFSET (0x0000001C)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_DAC_GAIN_REG_ADDR (0x03020A1C)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_REMOTE_CALIBRATION_0__REG_OFFSET (0x00000040)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_REMOTE_CALIBRATION_0__REG_ADDR (0x03020A40)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_REMOTE_CALIBRATION_1__REG_OFFSET (0x00000044)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_REMOTE_CALIBRATION_1__REG_ADDR (0x03020A44)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_REMOTE_CALIBRATION_2__REG_OFFSET (0x00000048)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_REMOTE_CALIBRATION_2__REG_ADDR (0x03020A48)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_REMOTE_CALIBRATION_3__REG_OFFSET (0x0000004C)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_REMOTE_CALIBRATION_3__REG_ADDR (0x03020A4C)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_REMOTE_CALIBRATION_4__REG_OFFSET (0x00000050)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_REMOTE_CALIBRATION_4__REG_ADDR (0x03020A50)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_REMOTE_CALIBRATION_5__REG_OFFSET (0x00000054)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_REMOTE_CALIBRATION_5__REG_ADDR (0x03020A54)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_REMOTE_CALIBRATION_6__REG_OFFSET (0x00000058)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_REMOTE_CALIBRATION_6__REG_ADDR (0x03020A58)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_REMOTE_CALIBRATION_7__REG_OFFSET (0x0000005C)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_REMOTE_CALIBRATION_7__REG_ADDR (0x03020A5C)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_REMOTE_CALIBRATION_8__REG_OFFSET (0x00000060)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_REMOTE_CALIBRATION_8__REG_ADDR (0x03020A60)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_REMOTE_CALIBRATION_9__REG_OFFSET (0x00000064)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_REMOTE_CALIBRATION_9__REG_ADDR (0x03020A64)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_REMOTE_CALIBRATION_10__REG_OFFSET (0x00000068)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_REMOTE_CALIBRATION_10__REG_ADDR (0x03020A68)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_REMOTE_CALIBRATION_11__REG_OFFSET (0x0000006C)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_REMOTE_CALIBRATION_11__REG_ADDR (0x03020A6C)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_REMOTE_CALIBRATION_12__REG_OFFSET (0x00000070)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_REMOTE_CALIBRATION_12__REG_ADDR (0x03020A70)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_REMOTE_CALIBRATION_13__REG_OFFSET (0x00000074)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_REMOTE_CALIBRATION_13__REG_ADDR (0x03020A74)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_REMOTE_CALIBRATION_14__REG_OFFSET (0x00000078)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_REMOTE_CALIBRATION_14__REG_ADDR (0x03020A78)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_REMOTE_CALIBRATION_15__REG_OFFSET (0x0000007C)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_REMOTE_CALIBRATION_15__REG_ADDR (0x03020A7C)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_REMOTE_SENSOR_DATA_0_REG_OFFSET (0x00000080)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_REMOTE_SENSOR_DATA_0_REG_ADDR (0x03020A80)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_REMOTE_SENSOR_DATA_1_REG_OFFSET (0x00000084)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_REMOTE_SENSOR_DATA_1_REG_ADDR (0x03020A84)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_REMOTE_SENSOR_DATA_2_REG_OFFSET (0x00000088)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_REMOTE_SENSOR_DATA_2_REG_ADDR (0x03020A88)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_REMOTE_SENSOR_DATA_3_REG_OFFSET (0x0000008C)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_REMOTE_SENSOR_DATA_3_REG_ADDR (0x03020A8C)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_REMOTE_SENSOR_DATA_4_REG_OFFSET (0x00000090)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_REMOTE_SENSOR_DATA_4_REG_ADDR (0x03020A90)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_REMOTE_SENSOR_DATA_5_REG_OFFSET (0x00000094)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_REMOTE_SENSOR_DATA_5_REG_ADDR (0x03020A94)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_REMOTE_SENSOR_DATA_6_REG_OFFSET (0x00000098)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_REMOTE_SENSOR_DATA_6_REG_ADDR (0x03020A98)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_REMOTE_SENSOR_DATA_7_REG_OFFSET (0x0000009C)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_REMOTE_SENSOR_DATA_7_REG_ADDR (0x03020A9C)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_REMOTE_SENSOR_DATA_8_REG_OFFSET (0x000000A0)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_REMOTE_SENSOR_DATA_8_REG_ADDR (0x03020AA0)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_REMOTE_SENSOR_DATA_9_REG_OFFSET (0x000000A4)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_REMOTE_SENSOR_DATA_9_REG_ADDR (0x03020AA4)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_REMOTE_SENSOR_DATA_10_REG_OFFSET (0x000000A8)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_REMOTE_SENSOR_DATA_10_REG_ADDR (0x03020AA8)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_REMOTE_SENSOR_DATA_11_REG_OFFSET (0x000000AC)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_REMOTE_SENSOR_DATA_11_REG_ADDR (0x03020AAC)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_REMOTE_SENSOR_DATA_12_REG_OFFSET (0x000000B0)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_REMOTE_SENSOR_DATA_12_REG_ADDR (0x03020AB0)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_REMOTE_SENSOR_DATA_13_REG_OFFSET (0x000000B4)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_REMOTE_SENSOR_DATA_13_REG_ADDR (0x03020AB4)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_REMOTE_SENSOR_DATA_14_REG_OFFSET (0x000000B8)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_REMOTE_SENSOR_DATA_14_REG_ADDR (0x03020AB8)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_REMOTE_SENSOR_DATA_15_REG_OFFSET (0x000000BC)
#define TT_NEO_AWM_WRAP_TEMP_SENSOR_REMOTE_SENSOR_DATA_15_REG_ADDR (0x03020ABC)

//==============================================================================
// Addresses for Address Map: tt_t6l1_slv
//==============================================================================

#define TT_T6L1_SLV_REG_MAP_BASE_ADDR (0x03800000)
#define TT_T6L1_SLV_REG_MAP_SIZE (0x00400000)

//==============================================================================
// Memory: t6l1_mem_port
//==============================================================================

#define TT_T6L1_SLV_T6L1_MEM_PORT_MEM_BASE_ADDR (0x03800000)
#define TT_T6L1_SLV_T6L1_MEM_PORT_MEM_SIZE (0x00400000)

//==============================================================================
// Addresses for Address Map: bus_error_unit_0
//==============================================================================

#define BUS_ERROR_UNIT_0_REG_MAP_BASE_ADDR (0x04000000)
#define BUS_ERROR_UNIT_0_REG_MAP_SIZE (0x00000030)

#define BUS_ERROR_UNIT_0_CAUSE_REG_OFFSET (0x00000000)
#define BUS_ERROR_UNIT_0_CAUSE_REG_ADDR (0x04000000)
#define BUS_ERROR_UNIT_0_PHYS_ADDR_REG_OFFSET (0x00000008)
#define BUS_ERROR_UNIT_0_PHYS_ADDR_REG_ADDR (0x04000008)
#define BUS_ERROR_UNIT_0_ENABLE_REG_OFFSET (0x00000010)
#define BUS_ERROR_UNIT_0_ENABLE_REG_ADDR (0x04000010)
#define BUS_ERROR_UNIT_0_PLIC_ENABLE_REG_OFFSET (0x00000018)
#define BUS_ERROR_UNIT_0_PLIC_ENABLE_REG_ADDR (0x04000018)
#define BUS_ERROR_UNIT_0_ACCRUED_REG_OFFSET (0x00000020)
#define BUS_ERROR_UNIT_0_ACCRUED_REG_ADDR (0x04000020)
#define BUS_ERROR_UNIT_0_LOCAL_ENABLE_REG_OFFSET (0x00000028)
#define BUS_ERROR_UNIT_0_LOCAL_ENABLE_REG_ADDR (0x04000028)

//==============================================================================
// Addresses for Address Map: bus_error_unit_1
//==============================================================================

#define BUS_ERROR_UNIT_1_REG_MAP_BASE_ADDR (0x04001000)
#define BUS_ERROR_UNIT_1_REG_MAP_SIZE (0x00000030)

#define BUS_ERROR_UNIT_1_CAUSE_REG_OFFSET (0x00000000)
#define BUS_ERROR_UNIT_1_CAUSE_REG_ADDR (0x04001000)
#define BUS_ERROR_UNIT_1_PHYS_ADDR_REG_OFFSET (0x00000008)
#define BUS_ERROR_UNIT_1_PHYS_ADDR_REG_ADDR (0x04001008)
#define BUS_ERROR_UNIT_1_ENABLE_REG_OFFSET (0x00000010)
#define BUS_ERROR_UNIT_1_ENABLE_REG_ADDR (0x04001010)
#define BUS_ERROR_UNIT_1_PLIC_ENABLE_REG_OFFSET (0x00000018)
#define BUS_ERROR_UNIT_1_PLIC_ENABLE_REG_ADDR (0x04001018)
#define BUS_ERROR_UNIT_1_ACCRUED_REG_OFFSET (0x00000020)
#define BUS_ERROR_UNIT_1_ACCRUED_REG_ADDR (0x04001020)
#define BUS_ERROR_UNIT_1_LOCAL_ENABLE_REG_OFFSET (0x00000028)
#define BUS_ERROR_UNIT_1_LOCAL_ENABLE_REG_ADDR (0x04001028)

//==============================================================================
// Addresses for Address Map: bus_error_unit_2
//==============================================================================

#define BUS_ERROR_UNIT_2_REG_MAP_BASE_ADDR (0x04002000)
#define BUS_ERROR_UNIT_2_REG_MAP_SIZE (0x00000030)

#define BUS_ERROR_UNIT_2_CAUSE_REG_OFFSET (0x00000000)
#define BUS_ERROR_UNIT_2_CAUSE_REG_ADDR (0x04002000)
#define BUS_ERROR_UNIT_2_PHYS_ADDR_REG_OFFSET (0x00000008)
#define BUS_ERROR_UNIT_2_PHYS_ADDR_REG_ADDR (0x04002008)
#define BUS_ERROR_UNIT_2_ENABLE_REG_OFFSET (0x00000010)
#define BUS_ERROR_UNIT_2_ENABLE_REG_ADDR (0x04002010)
#define BUS_ERROR_UNIT_2_PLIC_ENABLE_REG_OFFSET (0x00000018)
#define BUS_ERROR_UNIT_2_PLIC_ENABLE_REG_ADDR (0x04002018)
#define BUS_ERROR_UNIT_2_ACCRUED_REG_OFFSET (0x00000020)
#define BUS_ERROR_UNIT_2_ACCRUED_REG_ADDR (0x04002020)
#define BUS_ERROR_UNIT_2_LOCAL_ENABLE_REG_OFFSET (0x00000028)
#define BUS_ERROR_UNIT_2_LOCAL_ENABLE_REG_ADDR (0x04002028)

//==============================================================================
// Addresses for Address Map: bus_error_unit_3
//==============================================================================

#define BUS_ERROR_UNIT_3_REG_MAP_BASE_ADDR (0x04003000)
#define BUS_ERROR_UNIT_3_REG_MAP_SIZE (0x00000030)

#define BUS_ERROR_UNIT_3_CAUSE_REG_OFFSET (0x00000000)
#define BUS_ERROR_UNIT_3_CAUSE_REG_ADDR (0x04003000)
#define BUS_ERROR_UNIT_3_PHYS_ADDR_REG_OFFSET (0x00000008)
#define BUS_ERROR_UNIT_3_PHYS_ADDR_REG_ADDR (0x04003008)
#define BUS_ERROR_UNIT_3_ENABLE_REG_OFFSET (0x00000010)
#define BUS_ERROR_UNIT_3_ENABLE_REG_ADDR (0x04003010)
#define BUS_ERROR_UNIT_3_PLIC_ENABLE_REG_OFFSET (0x00000018)
#define BUS_ERROR_UNIT_3_PLIC_ENABLE_REG_ADDR (0x04003018)
#define BUS_ERROR_UNIT_3_ACCRUED_REG_OFFSET (0x00000020)
#define BUS_ERROR_UNIT_3_ACCRUED_REG_ADDR (0x04003020)
#define BUS_ERROR_UNIT_3_LOCAL_ENABLE_REG_OFFSET (0x00000028)
#define BUS_ERROR_UNIT_3_LOCAL_ENABLE_REG_ADDR (0x04003028)

//==============================================================================
// Addresses for Address Map: bus_error_unit_4
//==============================================================================

#define BUS_ERROR_UNIT_4_REG_MAP_BASE_ADDR (0x04004000)
#define BUS_ERROR_UNIT_4_REG_MAP_SIZE (0x00000030)

#define BUS_ERROR_UNIT_4_CAUSE_REG_OFFSET (0x00000000)
#define BUS_ERROR_UNIT_4_CAUSE_REG_ADDR (0x04004000)
#define BUS_ERROR_UNIT_4_PHYS_ADDR_REG_OFFSET (0x00000008)
#define BUS_ERROR_UNIT_4_PHYS_ADDR_REG_ADDR (0x04004008)
#define BUS_ERROR_UNIT_4_ENABLE_REG_OFFSET (0x00000010)
#define BUS_ERROR_UNIT_4_ENABLE_REG_ADDR (0x04004010)
#define BUS_ERROR_UNIT_4_PLIC_ENABLE_REG_OFFSET (0x00000018)
#define BUS_ERROR_UNIT_4_PLIC_ENABLE_REG_ADDR (0x04004018)
#define BUS_ERROR_UNIT_4_ACCRUED_REG_OFFSET (0x00000020)
#define BUS_ERROR_UNIT_4_ACCRUED_REG_ADDR (0x04004020)
#define BUS_ERROR_UNIT_4_LOCAL_ENABLE_REG_OFFSET (0x00000028)
#define BUS_ERROR_UNIT_4_LOCAL_ENABLE_REG_ADDR (0x04004028)

//==============================================================================
// Addresses for Address Map: bus_error_unit_5
//==============================================================================

#define BUS_ERROR_UNIT_5_REG_MAP_BASE_ADDR (0x04005000)
#define BUS_ERROR_UNIT_5_REG_MAP_SIZE (0x00000030)

#define BUS_ERROR_UNIT_5_CAUSE_REG_OFFSET (0x00000000)
#define BUS_ERROR_UNIT_5_CAUSE_REG_ADDR (0x04005000)
#define BUS_ERROR_UNIT_5_PHYS_ADDR_REG_OFFSET (0x00000008)
#define BUS_ERROR_UNIT_5_PHYS_ADDR_REG_ADDR (0x04005008)
#define BUS_ERROR_UNIT_5_ENABLE_REG_OFFSET (0x00000010)
#define BUS_ERROR_UNIT_5_ENABLE_REG_ADDR (0x04005010)
#define BUS_ERROR_UNIT_5_PLIC_ENABLE_REG_OFFSET (0x00000018)
#define BUS_ERROR_UNIT_5_PLIC_ENABLE_REG_ADDR (0x04005018)
#define BUS_ERROR_UNIT_5_ACCRUED_REG_OFFSET (0x00000020)
#define BUS_ERROR_UNIT_5_ACCRUED_REG_ADDR (0x04005020)
#define BUS_ERROR_UNIT_5_LOCAL_ENABLE_REG_OFFSET (0x00000028)
#define BUS_ERROR_UNIT_5_LOCAL_ENABLE_REG_ADDR (0x04005028)

//==============================================================================
// Addresses for Address Map: bus_error_unit_6
//==============================================================================

#define BUS_ERROR_UNIT_6_REG_MAP_BASE_ADDR (0x04006000)
#define BUS_ERROR_UNIT_6_REG_MAP_SIZE (0x00000030)

#define BUS_ERROR_UNIT_6_CAUSE_REG_OFFSET (0x00000000)
#define BUS_ERROR_UNIT_6_CAUSE_REG_ADDR (0x04006000)
#define BUS_ERROR_UNIT_6_PHYS_ADDR_REG_OFFSET (0x00000008)
#define BUS_ERROR_UNIT_6_PHYS_ADDR_REG_ADDR (0x04006008)
#define BUS_ERROR_UNIT_6_ENABLE_REG_OFFSET (0x00000010)
#define BUS_ERROR_UNIT_6_ENABLE_REG_ADDR (0x04006010)
#define BUS_ERROR_UNIT_6_PLIC_ENABLE_REG_OFFSET (0x00000018)
#define BUS_ERROR_UNIT_6_PLIC_ENABLE_REG_ADDR (0x04006018)
#define BUS_ERROR_UNIT_6_ACCRUED_REG_OFFSET (0x00000020)
#define BUS_ERROR_UNIT_6_ACCRUED_REG_ADDR (0x04006020)
#define BUS_ERROR_UNIT_6_LOCAL_ENABLE_REG_OFFSET (0x00000028)
#define BUS_ERROR_UNIT_6_LOCAL_ENABLE_REG_ADDR (0x04006028)

//==============================================================================
// Addresses for Address Map: bus_error_unit_7
//==============================================================================

#define BUS_ERROR_UNIT_7_REG_MAP_BASE_ADDR (0x04007000)
#define BUS_ERROR_UNIT_7_REG_MAP_SIZE (0x00000030)

#define BUS_ERROR_UNIT_7_CAUSE_REG_OFFSET (0x00000000)
#define BUS_ERROR_UNIT_7_CAUSE_REG_ADDR (0x04007000)
#define BUS_ERROR_UNIT_7_PHYS_ADDR_REG_OFFSET (0x00000008)
#define BUS_ERROR_UNIT_7_PHYS_ADDR_REG_ADDR (0x04007008)
#define BUS_ERROR_UNIT_7_ENABLE_REG_OFFSET (0x00000010)
#define BUS_ERROR_UNIT_7_ENABLE_REG_ADDR (0x04007010)
#define BUS_ERROR_UNIT_7_PLIC_ENABLE_REG_OFFSET (0x00000018)
#define BUS_ERROR_UNIT_7_PLIC_ENABLE_REG_ADDR (0x04007018)
#define BUS_ERROR_UNIT_7_ACCRUED_REG_OFFSET (0x00000020)
#define BUS_ERROR_UNIT_7_ACCRUED_REG_ADDR (0x04007020)
#define BUS_ERROR_UNIT_7_LOCAL_ENABLE_REG_OFFSET (0x00000028)
#define BUS_ERROR_UNIT_7_LOCAL_ENABLE_REG_ADDR (0x04007028)

//==============================================================================
// Addresses for Address Map: tt_cluster_core0_wdt
//==============================================================================

#define TT_CLUSTER_CORE0_WDT_REG_MAP_BASE_ADDR (0x04008000)
#define TT_CLUSTER_CORE0_WDT_REG_MAP_SIZE (0x00000024)

#define TT_CLUSTER_CORE0_WDT_CTRL_REG_OFFSET (0x00000000)
#define TT_CLUSTER_CORE0_WDT_CTRL_REG_ADDR (0x04008000)
#define TT_CLUSTER_CORE0_WDT_COUNT_REG_OFFSET (0x00000008)
#define TT_CLUSTER_CORE0_WDT_COUNT_REG_ADDR (0x04008008)
#define TT_CLUSTER_CORE0_WDT_SCALED_COUNT_REG_OFFSET (0x00000010)
#define TT_CLUSTER_CORE0_WDT_SCALED_COUNT_REG_ADDR (0x04008010)
#define TT_CLUSTER_CORE0_WDT_FEED_REG_OFFSET (0x00000018)
#define TT_CLUSTER_CORE0_WDT_FEED_REG_ADDR (0x04008018)
#define TT_CLUSTER_CORE0_WDT_KEY_REG_OFFSET (0x0000001C)
#define TT_CLUSTER_CORE0_WDT_KEY_REG_ADDR (0x0400801C)
#define TT_CLUSTER_CORE0_WDT_CMP_REG_OFFSET (0x00000020)
#define TT_CLUSTER_CORE0_WDT_CMP_REG_ADDR (0x04008020)

//==============================================================================
// Addresses for Address Map: tt_cluster_core1_wdt
//==============================================================================

#define TT_CLUSTER_CORE1_WDT_REG_MAP_BASE_ADDR (0x04009000)
#define TT_CLUSTER_CORE1_WDT_REG_MAP_SIZE (0x00000024)

#define TT_CLUSTER_CORE1_WDT_CTRL_REG_OFFSET (0x00000000)
#define TT_CLUSTER_CORE1_WDT_CTRL_REG_ADDR (0x04009000)
#define TT_CLUSTER_CORE1_WDT_COUNT_REG_OFFSET (0x00000008)
#define TT_CLUSTER_CORE1_WDT_COUNT_REG_ADDR (0x04009008)
#define TT_CLUSTER_CORE1_WDT_SCALED_COUNT_REG_OFFSET (0x00000010)
#define TT_CLUSTER_CORE1_WDT_SCALED_COUNT_REG_ADDR (0x04009010)
#define TT_CLUSTER_CORE1_WDT_FEED_REG_OFFSET (0x00000018)
#define TT_CLUSTER_CORE1_WDT_FEED_REG_ADDR (0x04009018)
#define TT_CLUSTER_CORE1_WDT_KEY_REG_OFFSET (0x0000001C)
#define TT_CLUSTER_CORE1_WDT_KEY_REG_ADDR (0x0400901C)
#define TT_CLUSTER_CORE1_WDT_CMP_REG_OFFSET (0x00000020)
#define TT_CLUSTER_CORE1_WDT_CMP_REG_ADDR (0x04009020)

//==============================================================================
// Addresses for Address Map: tt_cluster_core2_wdt
//==============================================================================

#define TT_CLUSTER_CORE2_WDT_REG_MAP_BASE_ADDR (0x0400A000)
#define TT_CLUSTER_CORE2_WDT_REG_MAP_SIZE (0x00000024)

#define TT_CLUSTER_CORE2_WDT_CTRL_REG_OFFSET (0x00000000)
#define TT_CLUSTER_CORE2_WDT_CTRL_REG_ADDR (0x0400A000)
#define TT_CLUSTER_CORE2_WDT_COUNT_REG_OFFSET (0x00000008)
#define TT_CLUSTER_CORE2_WDT_COUNT_REG_ADDR (0x0400A008)
#define TT_CLUSTER_CORE2_WDT_SCALED_COUNT_REG_OFFSET (0x00000010)
#define TT_CLUSTER_CORE2_WDT_SCALED_COUNT_REG_ADDR (0x0400A010)
#define TT_CLUSTER_CORE2_WDT_FEED_REG_OFFSET (0x00000018)
#define TT_CLUSTER_CORE2_WDT_FEED_REG_ADDR (0x0400A018)
#define TT_CLUSTER_CORE2_WDT_KEY_REG_OFFSET (0x0000001C)
#define TT_CLUSTER_CORE2_WDT_KEY_REG_ADDR (0x0400A01C)
#define TT_CLUSTER_CORE2_WDT_CMP_REG_OFFSET (0x00000020)
#define TT_CLUSTER_CORE2_WDT_CMP_REG_ADDR (0x0400A020)

//==============================================================================
// Addresses for Address Map: tt_cluster_core3_wdt
//==============================================================================

#define TT_CLUSTER_CORE3_WDT_REG_MAP_BASE_ADDR (0x0400B000)
#define TT_CLUSTER_CORE3_WDT_REG_MAP_SIZE (0x00000024)

#define TT_CLUSTER_CORE3_WDT_CTRL_REG_OFFSET (0x00000000)
#define TT_CLUSTER_CORE3_WDT_CTRL_REG_ADDR (0x0400B000)
#define TT_CLUSTER_CORE3_WDT_COUNT_REG_OFFSET (0x00000008)
#define TT_CLUSTER_CORE3_WDT_COUNT_REG_ADDR (0x0400B008)
#define TT_CLUSTER_CORE3_WDT_SCALED_COUNT_REG_OFFSET (0x00000010)
#define TT_CLUSTER_CORE3_WDT_SCALED_COUNT_REG_ADDR (0x0400B010)
#define TT_CLUSTER_CORE3_WDT_FEED_REG_OFFSET (0x00000018)
#define TT_CLUSTER_CORE3_WDT_FEED_REG_ADDR (0x0400B018)
#define TT_CLUSTER_CORE3_WDT_KEY_REG_OFFSET (0x0000001C)
#define TT_CLUSTER_CORE3_WDT_KEY_REG_ADDR (0x0400B01C)
#define TT_CLUSTER_CORE3_WDT_CMP_REG_OFFSET (0x00000020)
#define TT_CLUSTER_CORE3_WDT_CMP_REG_ADDR (0x0400B020)

//==============================================================================
// Addresses for Address Map: tt_cluster_core4_wdt
//==============================================================================

#define TT_CLUSTER_CORE4_WDT_REG_MAP_BASE_ADDR (0x0400C000)
#define TT_CLUSTER_CORE4_WDT_REG_MAP_SIZE (0x00000024)

#define TT_CLUSTER_CORE4_WDT_CTRL_REG_OFFSET (0x00000000)
#define TT_CLUSTER_CORE4_WDT_CTRL_REG_ADDR (0x0400C000)
#define TT_CLUSTER_CORE4_WDT_COUNT_REG_OFFSET (0x00000008)
#define TT_CLUSTER_CORE4_WDT_COUNT_REG_ADDR (0x0400C008)
#define TT_CLUSTER_CORE4_WDT_SCALED_COUNT_REG_OFFSET (0x00000010)
#define TT_CLUSTER_CORE4_WDT_SCALED_COUNT_REG_ADDR (0x0400C010)
#define TT_CLUSTER_CORE4_WDT_FEED_REG_OFFSET (0x00000018)
#define TT_CLUSTER_CORE4_WDT_FEED_REG_ADDR (0x0400C018)
#define TT_CLUSTER_CORE4_WDT_KEY_REG_OFFSET (0x0000001C)
#define TT_CLUSTER_CORE4_WDT_KEY_REG_ADDR (0x0400C01C)
#define TT_CLUSTER_CORE4_WDT_CMP_REG_OFFSET (0x00000020)
#define TT_CLUSTER_CORE4_WDT_CMP_REG_ADDR (0x0400C020)

//==============================================================================
// Addresses for Address Map: tt_cluster_core5_wdt
//==============================================================================

#define TT_CLUSTER_CORE5_WDT_REG_MAP_BASE_ADDR (0x0400D000)
#define TT_CLUSTER_CORE5_WDT_REG_MAP_SIZE (0x00000024)

#define TT_CLUSTER_CORE5_WDT_CTRL_REG_OFFSET (0x00000000)
#define TT_CLUSTER_CORE5_WDT_CTRL_REG_ADDR (0x0400D000)
#define TT_CLUSTER_CORE5_WDT_COUNT_REG_OFFSET (0x00000008)
#define TT_CLUSTER_CORE5_WDT_COUNT_REG_ADDR (0x0400D008)
#define TT_CLUSTER_CORE5_WDT_SCALED_COUNT_REG_OFFSET (0x00000010)
#define TT_CLUSTER_CORE5_WDT_SCALED_COUNT_REG_ADDR (0x0400D010)
#define TT_CLUSTER_CORE5_WDT_FEED_REG_OFFSET (0x00000018)
#define TT_CLUSTER_CORE5_WDT_FEED_REG_ADDR (0x0400D018)
#define TT_CLUSTER_CORE5_WDT_KEY_REG_OFFSET (0x0000001C)
#define TT_CLUSTER_CORE5_WDT_KEY_REG_ADDR (0x0400D01C)
#define TT_CLUSTER_CORE5_WDT_CMP_REG_OFFSET (0x00000020)
#define TT_CLUSTER_CORE5_WDT_CMP_REG_ADDR (0x0400D020)

//==============================================================================
// Addresses for Address Map: tt_cluster_core6_wdt
//==============================================================================

#define TT_CLUSTER_CORE6_WDT_REG_MAP_BASE_ADDR (0x0400E000)
#define TT_CLUSTER_CORE6_WDT_REG_MAP_SIZE (0x00000024)

#define TT_CLUSTER_CORE6_WDT_CTRL_REG_OFFSET (0x00000000)
#define TT_CLUSTER_CORE6_WDT_CTRL_REG_ADDR (0x0400E000)
#define TT_CLUSTER_CORE6_WDT_COUNT_REG_OFFSET (0x00000008)
#define TT_CLUSTER_CORE6_WDT_COUNT_REG_ADDR (0x0400E008)
#define TT_CLUSTER_CORE6_WDT_SCALED_COUNT_REG_OFFSET (0x00000010)
#define TT_CLUSTER_CORE6_WDT_SCALED_COUNT_REG_ADDR (0x0400E010)
#define TT_CLUSTER_CORE6_WDT_FEED_REG_OFFSET (0x00000018)
#define TT_CLUSTER_CORE6_WDT_FEED_REG_ADDR (0x0400E018)
#define TT_CLUSTER_CORE6_WDT_KEY_REG_OFFSET (0x0000001C)
#define TT_CLUSTER_CORE6_WDT_KEY_REG_ADDR (0x0400E01C)
#define TT_CLUSTER_CORE6_WDT_CMP_REG_OFFSET (0x00000020)
#define TT_CLUSTER_CORE6_WDT_CMP_REG_ADDR (0x0400E020)

//==============================================================================
// Addresses for Address Map: tt_cluster_core7_wdt
//==============================================================================

#define TT_CLUSTER_CORE7_WDT_REG_MAP_BASE_ADDR (0x0400F000)
#define TT_CLUSTER_CORE7_WDT_REG_MAP_SIZE (0x00000024)

#define TT_CLUSTER_CORE7_WDT_CTRL_REG_OFFSET (0x00000000)
#define TT_CLUSTER_CORE7_WDT_CTRL_REG_ADDR (0x0400F000)
#define TT_CLUSTER_CORE7_WDT_COUNT_REG_OFFSET (0x00000008)
#define TT_CLUSTER_CORE7_WDT_COUNT_REG_ADDR (0x0400F008)
#define TT_CLUSTER_CORE7_WDT_SCALED_COUNT_REG_OFFSET (0x00000010)
#define TT_CLUSTER_CORE7_WDT_SCALED_COUNT_REG_ADDR (0x0400F010)
#define TT_CLUSTER_CORE7_WDT_FEED_REG_OFFSET (0x00000018)
#define TT_CLUSTER_CORE7_WDT_FEED_REG_ADDR (0x0400F018)
#define TT_CLUSTER_CORE7_WDT_KEY_REG_OFFSET (0x0000001C)
#define TT_CLUSTER_CORE7_WDT_KEY_REG_ADDR (0x0400F01C)
#define TT_CLUSTER_CORE7_WDT_CMP_REG_OFFSET (0x00000020)
#define TT_CLUSTER_CORE7_WDT_CMP_REG_ADDR (0x0400F020)

//==============================================================================
// Addresses for Address Map: tt_cache_controller
//==============================================================================

#define TT_CACHE_CONTROLLER_REG_MAP_BASE_ADDR (0x04010000)
#define TT_CACHE_CONTROLLER_REG_MAP_SIZE (0x00000304)

#define TT_CACHE_CONTROLLER_CONFIGURATION_REG_OFFSET (0x00000000)
#define TT_CACHE_CONTROLLER_CONFIGURATION_REG_ADDR (0x04010000)
#define TT_CACHE_CONTROLLER_FLUSH64_REG_OFFSET (0x00000200)
#define TT_CACHE_CONTROLLER_FLUSH64_REG_ADDR (0x04010200)
#define TT_CACHE_CONTROLLER_FLUSH32_REG_OFFSET (0x00000240)
#define TT_CACHE_CONTROLLER_FLUSH32_REG_ADDR (0x04010240)
#define TT_CACHE_CONTROLLER_INVALIDATE64_REG_OFFSET (0x00000280)
#define TT_CACHE_CONTROLLER_INVALIDATE64_REG_ADDR (0x04010280)
#define TT_CACHE_CONTROLLER_INVALIDATE32_REG_OFFSET (0x000002C0)
#define TT_CACHE_CONTROLLER_INVALIDATE32_REG_ADDR (0x040102C0)
#define TT_CACHE_CONTROLLER_FULLINVALIDATE_REG_OFFSET (0x00000300)
#define TT_CACHE_CONTROLLER_FULLINVALIDATE_REG_ADDR (0x04010300)

//==============================================================================
// Addresses for Address Map: tt_debug_module_sbus
//==============================================================================

#define TT_DEBUG_MODULE_SBUS_REG_MAP_BASE_ADDR (0x04011000)
#define TT_DEBUG_MODULE_SBUS_REG_MAP_SIZE (0x00000880)

#define TT_DEBUG_MODULE_SBUS_HALTED_REG_OFFSET (0x00000100)
#define TT_DEBUG_MODULE_SBUS_HALTED_REG_ADDR (0x04011100)
#define TT_DEBUG_MODULE_SBUS_GOING_REG_OFFSET (0x00000104)
#define TT_DEBUG_MODULE_SBUS_GOING_REG_ADDR (0x04011104)
#define TT_DEBUG_MODULE_SBUS_RESUMING_REG_OFFSET (0x00000108)
#define TT_DEBUG_MODULE_SBUS_RESUMING_REG_ADDR (0x04011108)
#define TT_DEBUG_MODULE_SBUS_EXCEPTION_REG_OFFSET (0x0000010C)
#define TT_DEBUG_MODULE_SBUS_EXCEPTION_REG_ADDR (0x0401110C)
#define TT_DEBUG_MODULE_SBUS_WHERETO_REG_OFFSET (0x00000300)
#define TT_DEBUG_MODULE_SBUS_WHERETO_REG_ADDR (0x04011300)
#define TT_DEBUG_MODULE_SBUS_ABSTRACT_REG_OFFSET (0x00000328)
#define TT_DEBUG_MODULE_SBUS_ABSTRACT_REG_ADDR (0x04011328)
#define TT_DEBUG_MODULE_SBUS_ABSTRACT_2_REG_OFFSET (0x00000338)
#define TT_DEBUG_MODULE_SBUS_ABSTRACT_2_REG_ADDR (0x04011338)
#define TT_DEBUG_MODULE_SBUS_PROGBUF_REG_OFFSET (0x0000033C)
#define TT_DEBUG_MODULE_SBUS_PROGBUF_REG_ADDR (0x0401133C)
#define TT_DEBUG_MODULE_SBUS_IMPEBREAK_REG_OFFSET (0x0000037C)
#define TT_DEBUG_MODULE_SBUS_IMPEBREAK_REG_ADDR (0x0401137C)
#define TT_DEBUG_MODULE_SBUS_DATA_REG_OFFSET (0x00000380)
#define TT_DEBUG_MODULE_SBUS_DATA_REG_ADDR (0x04011380)
#define TT_DEBUG_MODULE_SBUS_FLAGS_REG_OFFSET (0x00000400)
#define TT_DEBUG_MODULE_SBUS_FLAGS_REG_ADDR (0x04011400)
#define TT_DEBUG_MODULE_SBUS_ROM_REG_OFFSET (0x00000800)
#define TT_DEBUG_MODULE_SBUS_ROM_REG_ADDR (0x04011800)

//==============================================================================
// Addresses for Address Map: tt_cluster_clint
//==============================================================================

#define TT_CLUSTER_CLINT_REG_MAP_BASE_ADDR (0x04020000)
#define TT_CLUSTER_CLINT_REG_MAP_SIZE (0x0000C000)

#define TT_CLUSTER_CLINT_MSIP_0__REG_OFFSET (0x00000000)
#define TT_CLUSTER_CLINT_MSIP_0__REG_ADDR (0x04020000)
#define TT_CLUSTER_CLINT_MSIP_1__REG_OFFSET (0x00000004)
#define TT_CLUSTER_CLINT_MSIP_1__REG_ADDR (0x04020004)
#define TT_CLUSTER_CLINT_MSIP_2__REG_OFFSET (0x00000008)
#define TT_CLUSTER_CLINT_MSIP_2__REG_ADDR (0x04020008)
#define TT_CLUSTER_CLINT_MSIP_3__REG_OFFSET (0x0000000C)
#define TT_CLUSTER_CLINT_MSIP_3__REG_ADDR (0x0402000C)
#define TT_CLUSTER_CLINT_MSIP_4__REG_OFFSET (0x00000010)
#define TT_CLUSTER_CLINT_MSIP_4__REG_ADDR (0x04020010)
#define TT_CLUSTER_CLINT_MSIP_5__REG_OFFSET (0x00000014)
#define TT_CLUSTER_CLINT_MSIP_5__REG_ADDR (0x04020014)
#define TT_CLUSTER_CLINT_MSIP_6__REG_OFFSET (0x00000018)
#define TT_CLUSTER_CLINT_MSIP_6__REG_ADDR (0x04020018)
#define TT_CLUSTER_CLINT_MSIP_7__REG_OFFSET (0x0000001C)
#define TT_CLUSTER_CLINT_MSIP_7__REG_ADDR (0x0402001C)
#define TT_CLUSTER_CLINT_MTIMECMP_0__REG_OFFSET (0x00004000)
#define TT_CLUSTER_CLINT_MTIMECMP_0__REG_ADDR (0x04024000)
#define TT_CLUSTER_CLINT_MTIMECMP_1__REG_OFFSET (0x00004008)
#define TT_CLUSTER_CLINT_MTIMECMP_1__REG_ADDR (0x04024008)
#define TT_CLUSTER_CLINT_MTIMECMP_2__REG_OFFSET (0x00004010)
#define TT_CLUSTER_CLINT_MTIMECMP_2__REG_ADDR (0x04024010)
#define TT_CLUSTER_CLINT_MTIMECMP_3__REG_OFFSET (0x00004018)
#define TT_CLUSTER_CLINT_MTIMECMP_3__REG_ADDR (0x04024018)
#define TT_CLUSTER_CLINT_MTIMECMP_4__REG_OFFSET (0x00004020)
#define TT_CLUSTER_CLINT_MTIMECMP_4__REG_ADDR (0x04024020)
#define TT_CLUSTER_CLINT_MTIMECMP_5__REG_OFFSET (0x00004028)
#define TT_CLUSTER_CLINT_MTIMECMP_5__REG_ADDR (0x04024028)
#define TT_CLUSTER_CLINT_MTIMECMP_6__REG_OFFSET (0x00004030)
#define TT_CLUSTER_CLINT_MTIMECMP_6__REG_ADDR (0x04024030)
#define TT_CLUSTER_CLINT_MTIMECMP_7__REG_OFFSET (0x00004038)
#define TT_CLUSTER_CLINT_MTIMECMP_7__REG_ADDR (0x04024038)
#define TT_CLUSTER_CLINT_MTIME_REG_OFFSET (0x0000BFF8)
#define TT_CLUSTER_CLINT_MTIME_REG_ADDR (0x0402BFF8)

//==============================================================================
// Addresses for Address Map: tt_cluster_plic
//==============================================================================

#define TT_CLUSTER_PLIC_REG_MAP_BASE_ADDR (0x08000000)
#define TT_CLUSTER_PLIC_REG_MAP_SIZE (0x00207008)

#define TT_CLUSTER_PLIC_PRIORITY_0__REG_OFFSET (0x00000004)
#define TT_CLUSTER_PLIC_PRIORITY_0__REG_ADDR (0x08000004)
#define TT_CLUSTER_PLIC_PRIORITY_1__REG_OFFSET (0x00000008)
#define TT_CLUSTER_PLIC_PRIORITY_1__REG_ADDR (0x08000008)
#define TT_CLUSTER_PLIC_PRIORITY_2__REG_OFFSET (0x0000000C)
#define TT_CLUSTER_PLIC_PRIORITY_2__REG_ADDR (0x0800000C)
#define TT_CLUSTER_PLIC_PRIORITY_3__REG_OFFSET (0x00000010)
#define TT_CLUSTER_PLIC_PRIORITY_3__REG_ADDR (0x08000010)
#define TT_CLUSTER_PLIC_PRIORITY_4__REG_OFFSET (0x00000014)
#define TT_CLUSTER_PLIC_PRIORITY_4__REG_ADDR (0x08000014)
#define TT_CLUSTER_PLIC_PRIORITY_5__REG_OFFSET (0x00000018)
#define TT_CLUSTER_PLIC_PRIORITY_5__REG_ADDR (0x08000018)
#define TT_CLUSTER_PLIC_PRIORITY_6__REG_OFFSET (0x0000001C)
#define TT_CLUSTER_PLIC_PRIORITY_6__REG_ADDR (0x0800001C)
#define TT_CLUSTER_PLIC_PRIORITY_7__REG_OFFSET (0x00000020)
#define TT_CLUSTER_PLIC_PRIORITY_7__REG_ADDR (0x08000020)
#define TT_CLUSTER_PLIC_PRIORITY_8__REG_OFFSET (0x00000024)
#define TT_CLUSTER_PLIC_PRIORITY_8__REG_ADDR (0x08000024)
#define TT_CLUSTER_PLIC_PRIORITY_9__REG_OFFSET (0x00000028)
#define TT_CLUSTER_PLIC_PRIORITY_9__REG_ADDR (0x08000028)
#define TT_CLUSTER_PLIC_PRIORITY_10__REG_OFFSET (0x0000002C)
#define TT_CLUSTER_PLIC_PRIORITY_10__REG_ADDR (0x0800002C)
#define TT_CLUSTER_PLIC_PRIORITY_11__REG_OFFSET (0x00000030)
#define TT_CLUSTER_PLIC_PRIORITY_11__REG_ADDR (0x08000030)
#define TT_CLUSTER_PLIC_PRIORITY_12__REG_OFFSET (0x00000034)
#define TT_CLUSTER_PLIC_PRIORITY_12__REG_ADDR (0x08000034)
#define TT_CLUSTER_PLIC_PRIORITY_13__REG_OFFSET (0x00000038)
#define TT_CLUSTER_PLIC_PRIORITY_13__REG_ADDR (0x08000038)
#define TT_CLUSTER_PLIC_PRIORITY_14__REG_OFFSET (0x0000003C)
#define TT_CLUSTER_PLIC_PRIORITY_14__REG_ADDR (0x0800003C)
#define TT_CLUSTER_PLIC_PRIORITY_15__REG_OFFSET (0x00000040)
#define TT_CLUSTER_PLIC_PRIORITY_15__REG_ADDR (0x08000040)
#define TT_CLUSTER_PLIC_PRIORITY_16__REG_OFFSET (0x00000044)
#define TT_CLUSTER_PLIC_PRIORITY_16__REG_ADDR (0x08000044)
#define TT_CLUSTER_PLIC_PRIORITY_17__REG_OFFSET (0x00000048)
#define TT_CLUSTER_PLIC_PRIORITY_17__REG_ADDR (0x08000048)
#define TT_CLUSTER_PLIC_PRIORITY_18__REG_OFFSET (0x0000004C)
#define TT_CLUSTER_PLIC_PRIORITY_18__REG_ADDR (0x0800004C)
#define TT_CLUSTER_PLIC_PRIORITY_19__REG_OFFSET (0x00000050)
#define TT_CLUSTER_PLIC_PRIORITY_19__REG_ADDR (0x08000050)
#define TT_CLUSTER_PLIC_PRIORITY_20__REG_OFFSET (0x00000054)
#define TT_CLUSTER_PLIC_PRIORITY_20__REG_ADDR (0x08000054)
#define TT_CLUSTER_PLIC_PRIORITY_21__REG_OFFSET (0x00000058)
#define TT_CLUSTER_PLIC_PRIORITY_21__REG_ADDR (0x08000058)
#define TT_CLUSTER_PLIC_PRIORITY_22__REG_OFFSET (0x0000005C)
#define TT_CLUSTER_PLIC_PRIORITY_22__REG_ADDR (0x0800005C)
#define TT_CLUSTER_PLIC_PRIORITY_23__REG_OFFSET (0x00000060)
#define TT_CLUSTER_PLIC_PRIORITY_23__REG_ADDR (0x08000060)
#define TT_CLUSTER_PLIC_PRIORITY_24__REG_OFFSET (0x00000064)
#define TT_CLUSTER_PLIC_PRIORITY_24__REG_ADDR (0x08000064)
#define TT_CLUSTER_PLIC_PRIORITY_25__REG_OFFSET (0x00000068)
#define TT_CLUSTER_PLIC_PRIORITY_25__REG_ADDR (0x08000068)
#define TT_CLUSTER_PLIC_PRIORITY_26__REG_OFFSET (0x0000006C)
#define TT_CLUSTER_PLIC_PRIORITY_26__REG_ADDR (0x0800006C)
#define TT_CLUSTER_PLIC_PRIORITY_27__REG_OFFSET (0x00000070)
#define TT_CLUSTER_PLIC_PRIORITY_27__REG_ADDR (0x08000070)
#define TT_CLUSTER_PLIC_PRIORITY_28__REG_OFFSET (0x00000074)
#define TT_CLUSTER_PLIC_PRIORITY_28__REG_ADDR (0x08000074)
#define TT_CLUSTER_PLIC_PRIORITY_29__REG_OFFSET (0x00000078)
#define TT_CLUSTER_PLIC_PRIORITY_29__REG_ADDR (0x08000078)
#define TT_CLUSTER_PLIC_PRIORITY_30__REG_OFFSET (0x0000007C)
#define TT_CLUSTER_PLIC_PRIORITY_30__REG_ADDR (0x0800007C)
#define TT_CLUSTER_PLIC_PRIORITY_31__REG_OFFSET (0x00000080)
#define TT_CLUSTER_PLIC_PRIORITY_31__REG_ADDR (0x08000080)
#define TT_CLUSTER_PLIC_PRIORITY_32__REG_OFFSET (0x00000084)
#define TT_CLUSTER_PLIC_PRIORITY_32__REG_ADDR (0x08000084)
#define TT_CLUSTER_PLIC_PRIORITY_33__REG_OFFSET (0x00000088)
#define TT_CLUSTER_PLIC_PRIORITY_33__REG_ADDR (0x08000088)
#define TT_CLUSTER_PLIC_PRIORITY_34__REG_OFFSET (0x0000008C)
#define TT_CLUSTER_PLIC_PRIORITY_34__REG_ADDR (0x0800008C)
#define TT_CLUSTER_PLIC_PRIORITY_35__REG_OFFSET (0x00000090)
#define TT_CLUSTER_PLIC_PRIORITY_35__REG_ADDR (0x08000090)
#define TT_CLUSTER_PLIC_PRIORITY_36__REG_OFFSET (0x00000094)
#define TT_CLUSTER_PLIC_PRIORITY_36__REG_ADDR (0x08000094)
#define TT_CLUSTER_PLIC_PRIORITY_37__REG_OFFSET (0x00000098)
#define TT_CLUSTER_PLIC_PRIORITY_37__REG_ADDR (0x08000098)
#define TT_CLUSTER_PLIC_PRIORITY_38__REG_OFFSET (0x0000009C)
#define TT_CLUSTER_PLIC_PRIORITY_38__REG_ADDR (0x0800009C)
#define TT_CLUSTER_PLIC_PRIORITY_39__REG_OFFSET (0x000000A0)
#define TT_CLUSTER_PLIC_PRIORITY_39__REG_ADDR (0x080000A0)
#define TT_CLUSTER_PLIC_PRIORITY_40__REG_OFFSET (0x000000A4)
#define TT_CLUSTER_PLIC_PRIORITY_40__REG_ADDR (0x080000A4)
#define TT_CLUSTER_PLIC_PRIORITY_41__REG_OFFSET (0x000000A8)
#define TT_CLUSTER_PLIC_PRIORITY_41__REG_ADDR (0x080000A8)
#define TT_CLUSTER_PLIC_PRIORITY_42__REG_OFFSET (0x000000AC)
#define TT_CLUSTER_PLIC_PRIORITY_42__REG_ADDR (0x080000AC)
#define TT_CLUSTER_PLIC_PRIORITY_43__REG_OFFSET (0x000000B0)
#define TT_CLUSTER_PLIC_PRIORITY_43__REG_ADDR (0x080000B0)
#define TT_CLUSTER_PLIC_PRIORITY_44__REG_OFFSET (0x000000B4)
#define TT_CLUSTER_PLIC_PRIORITY_44__REG_ADDR (0x080000B4)
#define TT_CLUSTER_PLIC_PRIORITY_45__REG_OFFSET (0x000000B8)
#define TT_CLUSTER_PLIC_PRIORITY_45__REG_ADDR (0x080000B8)
#define TT_CLUSTER_PLIC_PRIORITY_46__REG_OFFSET (0x000000BC)
#define TT_CLUSTER_PLIC_PRIORITY_46__REG_ADDR (0x080000BC)
#define TT_CLUSTER_PLIC_PRIORITY_47__REG_OFFSET (0x000000C0)
#define TT_CLUSTER_PLIC_PRIORITY_47__REG_ADDR (0x080000C0)
#define TT_CLUSTER_PLIC_PRIORITY_48__REG_OFFSET (0x000000C4)
#define TT_CLUSTER_PLIC_PRIORITY_48__REG_ADDR (0x080000C4)
#define TT_CLUSTER_PLIC_PRIORITY_49__REG_OFFSET (0x000000C8)
#define TT_CLUSTER_PLIC_PRIORITY_49__REG_ADDR (0x080000C8)
#define TT_CLUSTER_PLIC_PRIORITY_50__REG_OFFSET (0x000000CC)
#define TT_CLUSTER_PLIC_PRIORITY_50__REG_ADDR (0x080000CC)
#define TT_CLUSTER_PLIC_PRIORITY_51__REG_OFFSET (0x000000D0)
#define TT_CLUSTER_PLIC_PRIORITY_51__REG_ADDR (0x080000D0)
#define TT_CLUSTER_PLIC_PRIORITY_52__REG_OFFSET (0x000000D4)
#define TT_CLUSTER_PLIC_PRIORITY_52__REG_ADDR (0x080000D4)
#define TT_CLUSTER_PLIC_PRIORITY_53__REG_OFFSET (0x000000D8)
#define TT_CLUSTER_PLIC_PRIORITY_53__REG_ADDR (0x080000D8)
#define TT_CLUSTER_PLIC_PRIORITY_54__REG_OFFSET (0x000000DC)
#define TT_CLUSTER_PLIC_PRIORITY_54__REG_ADDR (0x080000DC)
#define TT_CLUSTER_PLIC_PRIORITY_55__REG_OFFSET (0x000000E0)
#define TT_CLUSTER_PLIC_PRIORITY_55__REG_ADDR (0x080000E0)
#define TT_CLUSTER_PLIC_PRIORITY_56__REG_OFFSET (0x000000E4)
#define TT_CLUSTER_PLIC_PRIORITY_56__REG_ADDR (0x080000E4)
#define TT_CLUSTER_PLIC_PRIORITY_57__REG_OFFSET (0x000000E8)
#define TT_CLUSTER_PLIC_PRIORITY_57__REG_ADDR (0x080000E8)
#define TT_CLUSTER_PLIC_PRIORITY_58__REG_OFFSET (0x000000EC)
#define TT_CLUSTER_PLIC_PRIORITY_58__REG_ADDR (0x080000EC)
#define TT_CLUSTER_PLIC_PRIORITY_59__REG_OFFSET (0x000000F0)
#define TT_CLUSTER_PLIC_PRIORITY_59__REG_ADDR (0x080000F0)
#define TT_CLUSTER_PLIC_PRIORITY_60__REG_OFFSET (0x000000F4)
#define TT_CLUSTER_PLIC_PRIORITY_60__REG_ADDR (0x080000F4)
#define TT_CLUSTER_PLIC_PRIORITY_61__REG_OFFSET (0x000000F8)
#define TT_CLUSTER_PLIC_PRIORITY_61__REG_ADDR (0x080000F8)
#define TT_CLUSTER_PLIC_PRIORITY_62__REG_OFFSET (0x000000FC)
#define TT_CLUSTER_PLIC_PRIORITY_62__REG_ADDR (0x080000FC)
#define TT_CLUSTER_PLIC_PRIORITY_63__REG_OFFSET (0x00000100)
#define TT_CLUSTER_PLIC_PRIORITY_63__REG_ADDR (0x08000100)
#define TT_CLUSTER_PLIC_PRIORITY_64__REG_OFFSET (0x00000104)
#define TT_CLUSTER_PLIC_PRIORITY_64__REG_ADDR (0x08000104)
#define TT_CLUSTER_PLIC_PRIORITY_65__REG_OFFSET (0x00000108)
#define TT_CLUSTER_PLIC_PRIORITY_65__REG_ADDR (0x08000108)
#define TT_CLUSTER_PLIC_PRIORITY_66__REG_OFFSET (0x0000010C)
#define TT_CLUSTER_PLIC_PRIORITY_66__REG_ADDR (0x0800010C)
#define TT_CLUSTER_PLIC_PRIORITY_67__REG_OFFSET (0x00000110)
#define TT_CLUSTER_PLIC_PRIORITY_67__REG_ADDR (0x08000110)
#define TT_CLUSTER_PLIC_PRIORITY_68__REG_OFFSET (0x00000114)
#define TT_CLUSTER_PLIC_PRIORITY_68__REG_ADDR (0x08000114)
#define TT_CLUSTER_PLIC_PRIORITY_69__REG_OFFSET (0x00000118)
#define TT_CLUSTER_PLIC_PRIORITY_69__REG_ADDR (0x08000118)
#define TT_CLUSTER_PLIC_PRIORITY_70__REG_OFFSET (0x0000011C)
#define TT_CLUSTER_PLIC_PRIORITY_70__REG_ADDR (0x0800011C)
#define TT_CLUSTER_PLIC_PRIORITY_71__REG_OFFSET (0x00000120)
#define TT_CLUSTER_PLIC_PRIORITY_71__REG_ADDR (0x08000120)
#define TT_CLUSTER_PLIC_PRIORITY_72__REG_OFFSET (0x00000124)
#define TT_CLUSTER_PLIC_PRIORITY_72__REG_ADDR (0x08000124)
#define TT_CLUSTER_PLIC_PRIORITY_73__REG_OFFSET (0x00000128)
#define TT_CLUSTER_PLIC_PRIORITY_73__REG_ADDR (0x08000128)
#define TT_CLUSTER_PLIC_PRIORITY_74__REG_OFFSET (0x0000012C)
#define TT_CLUSTER_PLIC_PRIORITY_74__REG_ADDR (0x0800012C)
#define TT_CLUSTER_PLIC_PRIORITY_75__REG_OFFSET (0x00000130)
#define TT_CLUSTER_PLIC_PRIORITY_75__REG_ADDR (0x08000130)
#define TT_CLUSTER_PLIC_PRIORITY_76__REG_OFFSET (0x00000134)
#define TT_CLUSTER_PLIC_PRIORITY_76__REG_ADDR (0x08000134)
#define TT_CLUSTER_PLIC_PRIORITY_77__REG_OFFSET (0x00000138)
#define TT_CLUSTER_PLIC_PRIORITY_77__REG_ADDR (0x08000138)
#define TT_CLUSTER_PLIC_PRIORITY_78__REG_OFFSET (0x0000013C)
#define TT_CLUSTER_PLIC_PRIORITY_78__REG_ADDR (0x0800013C)
#define TT_CLUSTER_PLIC_PRIORITY_79__REG_OFFSET (0x00000140)
#define TT_CLUSTER_PLIC_PRIORITY_79__REG_ADDR (0x08000140)
#define TT_CLUSTER_PLIC_PRIORITY_80__REG_OFFSET (0x00000144)
#define TT_CLUSTER_PLIC_PRIORITY_80__REG_ADDR (0x08000144)
#define TT_CLUSTER_PLIC_PRIORITY_81__REG_OFFSET (0x00000148)
#define TT_CLUSTER_PLIC_PRIORITY_81__REG_ADDR (0x08000148)
#define TT_CLUSTER_PLIC_PRIORITY_82__REG_OFFSET (0x0000014C)
#define TT_CLUSTER_PLIC_PRIORITY_82__REG_ADDR (0x0800014C)
#define TT_CLUSTER_PLIC_PRIORITY_83__REG_OFFSET (0x00000150)
#define TT_CLUSTER_PLIC_PRIORITY_83__REG_ADDR (0x08000150)
#define TT_CLUSTER_PLIC_PRIORITY_84__REG_OFFSET (0x00000154)
#define TT_CLUSTER_PLIC_PRIORITY_84__REG_ADDR (0x08000154)
#define TT_CLUSTER_PLIC_PRIORITY_85__REG_OFFSET (0x00000158)
#define TT_CLUSTER_PLIC_PRIORITY_85__REG_ADDR (0x08000158)
#define TT_CLUSTER_PLIC_PRIORITY_86__REG_OFFSET (0x0000015C)
#define TT_CLUSTER_PLIC_PRIORITY_86__REG_ADDR (0x0800015C)
#define TT_CLUSTER_PLIC_PRIORITY_87__REG_OFFSET (0x00000160)
#define TT_CLUSTER_PLIC_PRIORITY_87__REG_ADDR (0x08000160)
#define TT_CLUSTER_PLIC_PRIORITY_88__REG_OFFSET (0x00000164)
#define TT_CLUSTER_PLIC_PRIORITY_88__REG_ADDR (0x08000164)
#define TT_CLUSTER_PLIC_PRIORITY_89__REG_OFFSET (0x00000168)
#define TT_CLUSTER_PLIC_PRIORITY_89__REG_ADDR (0x08000168)
#define TT_CLUSTER_PLIC_PRIORITY_90__REG_OFFSET (0x0000016C)
#define TT_CLUSTER_PLIC_PRIORITY_90__REG_ADDR (0x0800016C)
#define TT_CLUSTER_PLIC_PRIORITY_91__REG_OFFSET (0x00000170)
#define TT_CLUSTER_PLIC_PRIORITY_91__REG_ADDR (0x08000170)
#define TT_CLUSTER_PLIC_PRIORITY_92__REG_OFFSET (0x00000174)
#define TT_CLUSTER_PLIC_PRIORITY_92__REG_ADDR (0x08000174)
#define TT_CLUSTER_PLIC_PRIORITY_93__REG_OFFSET (0x00000178)
#define TT_CLUSTER_PLIC_PRIORITY_93__REG_ADDR (0x08000178)
#define TT_CLUSTER_PLIC_PRIORITY_94__REG_OFFSET (0x0000017C)
#define TT_CLUSTER_PLIC_PRIORITY_94__REG_ADDR (0x0800017C)
#define TT_CLUSTER_PLIC_PRIORITY_95__REG_OFFSET (0x00000180)
#define TT_CLUSTER_PLIC_PRIORITY_95__REG_ADDR (0x08000180)
#define TT_CLUSTER_PLIC_PRIORITY_96__REG_OFFSET (0x00000184)
#define TT_CLUSTER_PLIC_PRIORITY_96__REG_ADDR (0x08000184)
#define TT_CLUSTER_PLIC_PRIORITY_97__REG_OFFSET (0x00000188)
#define TT_CLUSTER_PLIC_PRIORITY_97__REG_ADDR (0x08000188)
#define TT_CLUSTER_PLIC_PRIORITY_98__REG_OFFSET (0x0000018C)
#define TT_CLUSTER_PLIC_PRIORITY_98__REG_ADDR (0x0800018C)
#define TT_CLUSTER_PLIC_PRIORITY_99__REG_OFFSET (0x00000190)
#define TT_CLUSTER_PLIC_PRIORITY_99__REG_ADDR (0x08000190)
#define TT_CLUSTER_PLIC_PRIORITY_100__REG_OFFSET (0x00000194)
#define TT_CLUSTER_PLIC_PRIORITY_100__REG_ADDR (0x08000194)
#define TT_CLUSTER_PLIC_PRIORITY_101__REG_OFFSET (0x00000198)
#define TT_CLUSTER_PLIC_PRIORITY_101__REG_ADDR (0x08000198)
#define TT_CLUSTER_PLIC_PRIORITY_102__REG_OFFSET (0x0000019C)
#define TT_CLUSTER_PLIC_PRIORITY_102__REG_ADDR (0x0800019C)
#define TT_CLUSTER_PLIC_PRIORITY_103__REG_OFFSET (0x000001A0)
#define TT_CLUSTER_PLIC_PRIORITY_103__REG_ADDR (0x080001A0)
#define TT_CLUSTER_PLIC_PRIORITY_104__REG_OFFSET (0x000001A4)
#define TT_CLUSTER_PLIC_PRIORITY_104__REG_ADDR (0x080001A4)
#define TT_CLUSTER_PLIC_PRIORITY_105__REG_OFFSET (0x000001A8)
#define TT_CLUSTER_PLIC_PRIORITY_105__REG_ADDR (0x080001A8)
#define TT_CLUSTER_PLIC_PRIORITY_106__REG_OFFSET (0x000001AC)
#define TT_CLUSTER_PLIC_PRIORITY_106__REG_ADDR (0x080001AC)
#define TT_CLUSTER_PLIC_PRIORITY_107__REG_OFFSET (0x000001B0)
#define TT_CLUSTER_PLIC_PRIORITY_107__REG_ADDR (0x080001B0)
#define TT_CLUSTER_PLIC_PRIORITY_108__REG_OFFSET (0x000001B4)
#define TT_CLUSTER_PLIC_PRIORITY_108__REG_ADDR (0x080001B4)
#define TT_CLUSTER_PLIC_PRIORITY_109__REG_OFFSET (0x000001B8)
#define TT_CLUSTER_PLIC_PRIORITY_109__REG_ADDR (0x080001B8)
#define TT_CLUSTER_PLIC_PRIORITY_110__REG_OFFSET (0x000001BC)
#define TT_CLUSTER_PLIC_PRIORITY_110__REG_ADDR (0x080001BC)
#define TT_CLUSTER_PLIC_PRIORITY_111__REG_OFFSET (0x000001C0)
#define TT_CLUSTER_PLIC_PRIORITY_111__REG_ADDR (0x080001C0)
#define TT_CLUSTER_PLIC_PRIORITY_112__REG_OFFSET (0x000001C4)
#define TT_CLUSTER_PLIC_PRIORITY_112__REG_ADDR (0x080001C4)
#define TT_CLUSTER_PLIC_PRIORITY_113__REG_OFFSET (0x000001C8)
#define TT_CLUSTER_PLIC_PRIORITY_113__REG_ADDR (0x080001C8)
#define TT_CLUSTER_PLIC_PRIORITY_114__REG_OFFSET (0x000001CC)
#define TT_CLUSTER_PLIC_PRIORITY_114__REG_ADDR (0x080001CC)
#define TT_CLUSTER_PLIC_PRIORITY_115__REG_OFFSET (0x000001D0)
#define TT_CLUSTER_PLIC_PRIORITY_115__REG_ADDR (0x080001D0)
#define TT_CLUSTER_PLIC_PRIORITY_116__REG_OFFSET (0x000001D4)
#define TT_CLUSTER_PLIC_PRIORITY_116__REG_ADDR (0x080001D4)
#define TT_CLUSTER_PLIC_PRIORITY_117__REG_OFFSET (0x000001D8)
#define TT_CLUSTER_PLIC_PRIORITY_117__REG_ADDR (0x080001D8)
#define TT_CLUSTER_PLIC_PRIORITY_118__REG_OFFSET (0x000001DC)
#define TT_CLUSTER_PLIC_PRIORITY_118__REG_ADDR (0x080001DC)
#define TT_CLUSTER_PLIC_PRIORITY_119__REG_OFFSET (0x000001E0)
#define TT_CLUSTER_PLIC_PRIORITY_119__REG_ADDR (0x080001E0)
#define TT_CLUSTER_PLIC_PRIORITY_120__REG_OFFSET (0x000001E4)
#define TT_CLUSTER_PLIC_PRIORITY_120__REG_ADDR (0x080001E4)
#define TT_CLUSTER_PLIC_PRIORITY_121__REG_OFFSET (0x000001E8)
#define TT_CLUSTER_PLIC_PRIORITY_121__REG_ADDR (0x080001E8)
#define TT_CLUSTER_PLIC_PRIORITY_122__REG_OFFSET (0x000001EC)
#define TT_CLUSTER_PLIC_PRIORITY_122__REG_ADDR (0x080001EC)
#define TT_CLUSTER_PLIC_PRIORITY_123__REG_OFFSET (0x000001F0)
#define TT_CLUSTER_PLIC_PRIORITY_123__REG_ADDR (0x080001F0)
#define TT_CLUSTER_PLIC_PRIORITY_124__REG_OFFSET (0x000001F4)
#define TT_CLUSTER_PLIC_PRIORITY_124__REG_ADDR (0x080001F4)
#define TT_CLUSTER_PLIC_PRIORITY_125__REG_OFFSET (0x000001F8)
#define TT_CLUSTER_PLIC_PRIORITY_125__REG_ADDR (0x080001F8)
#define TT_CLUSTER_PLIC_PRIORITY_126__REG_OFFSET (0x000001FC)
#define TT_CLUSTER_PLIC_PRIORITY_126__REG_ADDR (0x080001FC)
#define TT_CLUSTER_PLIC_PRIORITY_127__REG_OFFSET (0x00000200)
#define TT_CLUSTER_PLIC_PRIORITY_127__REG_ADDR (0x08000200)
#define TT_CLUSTER_PLIC_PRIORITY_128__REG_OFFSET (0x00000204)
#define TT_CLUSTER_PLIC_PRIORITY_128__REG_ADDR (0x08000204)
#define TT_CLUSTER_PLIC_PRIORITY_129__REG_OFFSET (0x00000208)
#define TT_CLUSTER_PLIC_PRIORITY_129__REG_ADDR (0x08000208)
#define TT_CLUSTER_PLIC_PRIORITY_130__REG_OFFSET (0x0000020C)
#define TT_CLUSTER_PLIC_PRIORITY_130__REG_ADDR (0x0800020C)
#define TT_CLUSTER_PLIC_PRIORITY_131__REG_OFFSET (0x00000210)
#define TT_CLUSTER_PLIC_PRIORITY_131__REG_ADDR (0x08000210)
#define TT_CLUSTER_PLIC_PRIORITY_132__REG_OFFSET (0x00000214)
#define TT_CLUSTER_PLIC_PRIORITY_132__REG_ADDR (0x08000214)
#define TT_CLUSTER_PLIC_PRIORITY_133__REG_OFFSET (0x00000218)
#define TT_CLUSTER_PLIC_PRIORITY_133__REG_ADDR (0x08000218)
#define TT_CLUSTER_PLIC_PRIORITY_134__REG_OFFSET (0x0000021C)
#define TT_CLUSTER_PLIC_PRIORITY_134__REG_ADDR (0x0800021C)
#define TT_CLUSTER_PLIC_PRIORITY_135__REG_OFFSET (0x00000220)
#define TT_CLUSTER_PLIC_PRIORITY_135__REG_ADDR (0x08000220)
#define TT_CLUSTER_PLIC_PRIORITY_136__REG_OFFSET (0x00000224)
#define TT_CLUSTER_PLIC_PRIORITY_136__REG_ADDR (0x08000224)
#define TT_CLUSTER_PLIC_PRIORITY_137__REG_OFFSET (0x00000228)
#define TT_CLUSTER_PLIC_PRIORITY_137__REG_ADDR (0x08000228)
#define TT_CLUSTER_PLIC_PRIORITY_138__REG_OFFSET (0x0000022C)
#define TT_CLUSTER_PLIC_PRIORITY_138__REG_ADDR (0x0800022C)
#define TT_CLUSTER_PLIC_PRIORITY_139__REG_OFFSET (0x00000230)
#define TT_CLUSTER_PLIC_PRIORITY_139__REG_ADDR (0x08000230)
#define TT_CLUSTER_PLIC_PRIORITY_140__REG_OFFSET (0x00000234)
#define TT_CLUSTER_PLIC_PRIORITY_140__REG_ADDR (0x08000234)
#define TT_CLUSTER_PLIC_PRIORITY_141__REG_OFFSET (0x00000238)
#define TT_CLUSTER_PLIC_PRIORITY_141__REG_ADDR (0x08000238)
#define TT_CLUSTER_PLIC_PRIORITY_142__REG_OFFSET (0x0000023C)
#define TT_CLUSTER_PLIC_PRIORITY_142__REG_ADDR (0x0800023C)
#define TT_CLUSTER_PLIC_PRIORITY_143__REG_OFFSET (0x00000240)
#define TT_CLUSTER_PLIC_PRIORITY_143__REG_ADDR (0x08000240)
#define TT_CLUSTER_PLIC_PENDING_0__REG_OFFSET (0x00001000)
#define TT_CLUSTER_PLIC_PENDING_0__REG_ADDR (0x08001000)
#define TT_CLUSTER_PLIC_PENDING_1__REG_OFFSET (0x00001004)
#define TT_CLUSTER_PLIC_PENDING_1__REG_ADDR (0x08001004)
#define TT_CLUSTER_PLIC_PENDING_2__REG_OFFSET (0x00001008)
#define TT_CLUSTER_PLIC_PENDING_2__REG_ADDR (0x08001008)
#define TT_CLUSTER_PLIC_PENDING_3__REG_OFFSET (0x0000100C)
#define TT_CLUSTER_PLIC_PENDING_3__REG_ADDR (0x0800100C)
#define TT_CLUSTER_PLIC_PENDING_4__REG_OFFSET (0x00001010)
#define TT_CLUSTER_PLIC_PENDING_4__REG_ADDR (0x08001010)
#define TT_CLUSTER_PLIC_CORE0_IE_0__REG_OFFSET (0x00002000)
#define TT_CLUSTER_PLIC_CORE0_IE_0__REG_ADDR (0x08002000)
#define TT_CLUSTER_PLIC_CORE0_IE_1__REG_OFFSET (0x00002004)
#define TT_CLUSTER_PLIC_CORE0_IE_1__REG_ADDR (0x08002004)
#define TT_CLUSTER_PLIC_CORE0_IE_2__REG_OFFSET (0x00002008)
#define TT_CLUSTER_PLIC_CORE0_IE_2__REG_ADDR (0x08002008)
#define TT_CLUSTER_PLIC_CORE0_IE_3__REG_OFFSET (0x0000200C)
#define TT_CLUSTER_PLIC_CORE0_IE_3__REG_ADDR (0x0800200C)
#define TT_CLUSTER_PLIC_CORE0_IE_4__REG_OFFSET (0x00002010)
#define TT_CLUSTER_PLIC_CORE0_IE_4__REG_ADDR (0x08002010)
#define TT_CLUSTER_PLIC_CORE1_IE_0__REG_OFFSET (0x00002080)
#define TT_CLUSTER_PLIC_CORE1_IE_0__REG_ADDR (0x08002080)
#define TT_CLUSTER_PLIC_CORE1_IE_1__REG_OFFSET (0x00002084)
#define TT_CLUSTER_PLIC_CORE1_IE_1__REG_ADDR (0x08002084)
#define TT_CLUSTER_PLIC_CORE1_IE_2__REG_OFFSET (0x00002088)
#define TT_CLUSTER_PLIC_CORE1_IE_2__REG_ADDR (0x08002088)
#define TT_CLUSTER_PLIC_CORE1_IE_3__REG_OFFSET (0x0000208C)
#define TT_CLUSTER_PLIC_CORE1_IE_3__REG_ADDR (0x0800208C)
#define TT_CLUSTER_PLIC_CORE1_IE_4__REG_OFFSET (0x00002090)
#define TT_CLUSTER_PLIC_CORE1_IE_4__REG_ADDR (0x08002090)
#define TT_CLUSTER_PLIC_CORE2_IE_0__REG_OFFSET (0x00002100)
#define TT_CLUSTER_PLIC_CORE2_IE_0__REG_ADDR (0x08002100)
#define TT_CLUSTER_PLIC_CORE2_IE_1__REG_OFFSET (0x00002104)
#define TT_CLUSTER_PLIC_CORE2_IE_1__REG_ADDR (0x08002104)
#define TT_CLUSTER_PLIC_CORE2_IE_2__REG_OFFSET (0x00002108)
#define TT_CLUSTER_PLIC_CORE2_IE_2__REG_ADDR (0x08002108)
#define TT_CLUSTER_PLIC_CORE2_IE_3__REG_OFFSET (0x0000210C)
#define TT_CLUSTER_PLIC_CORE2_IE_3__REG_ADDR (0x0800210C)
#define TT_CLUSTER_PLIC_CORE2_IE_4__REG_OFFSET (0x00002110)
#define TT_CLUSTER_PLIC_CORE2_IE_4__REG_ADDR (0x08002110)
#define TT_CLUSTER_PLIC_CORE3_IE_0__REG_OFFSET (0x00002180)
#define TT_CLUSTER_PLIC_CORE3_IE_0__REG_ADDR (0x08002180)
#define TT_CLUSTER_PLIC_CORE3_IE_1__REG_OFFSET (0x00002184)
#define TT_CLUSTER_PLIC_CORE3_IE_1__REG_ADDR (0x08002184)
#define TT_CLUSTER_PLIC_CORE3_IE_2__REG_OFFSET (0x00002188)
#define TT_CLUSTER_PLIC_CORE3_IE_2__REG_ADDR (0x08002188)
#define TT_CLUSTER_PLIC_CORE3_IE_3__REG_OFFSET (0x0000218C)
#define TT_CLUSTER_PLIC_CORE3_IE_3__REG_ADDR (0x0800218C)
#define TT_CLUSTER_PLIC_CORE3_IE_4__REG_OFFSET (0x00002190)
#define TT_CLUSTER_PLIC_CORE3_IE_4__REG_ADDR (0x08002190)
#define TT_CLUSTER_PLIC_CORE4_IE_0__REG_OFFSET (0x00002200)
#define TT_CLUSTER_PLIC_CORE4_IE_0__REG_ADDR (0x08002200)
#define TT_CLUSTER_PLIC_CORE4_IE_1__REG_OFFSET (0x00002204)
#define TT_CLUSTER_PLIC_CORE4_IE_1__REG_ADDR (0x08002204)
#define TT_CLUSTER_PLIC_CORE4_IE_2__REG_OFFSET (0x00002208)
#define TT_CLUSTER_PLIC_CORE4_IE_2__REG_ADDR (0x08002208)
#define TT_CLUSTER_PLIC_CORE4_IE_3__REG_OFFSET (0x0000220C)
#define TT_CLUSTER_PLIC_CORE4_IE_3__REG_ADDR (0x0800220C)
#define TT_CLUSTER_PLIC_CORE4_IE_4__REG_OFFSET (0x00002210)
#define TT_CLUSTER_PLIC_CORE4_IE_4__REG_ADDR (0x08002210)
#define TT_CLUSTER_PLIC_CORE5_IE_0__REG_OFFSET (0x00002280)
#define TT_CLUSTER_PLIC_CORE5_IE_0__REG_ADDR (0x08002280)
#define TT_CLUSTER_PLIC_CORE5_IE_1__REG_OFFSET (0x00002284)
#define TT_CLUSTER_PLIC_CORE5_IE_1__REG_ADDR (0x08002284)
#define TT_CLUSTER_PLIC_CORE5_IE_2__REG_OFFSET (0x00002288)
#define TT_CLUSTER_PLIC_CORE5_IE_2__REG_ADDR (0x08002288)
#define TT_CLUSTER_PLIC_CORE5_IE_3__REG_OFFSET (0x0000228C)
#define TT_CLUSTER_PLIC_CORE5_IE_3__REG_ADDR (0x0800228C)
#define TT_CLUSTER_PLIC_CORE5_IE_4__REG_OFFSET (0x00002290)
#define TT_CLUSTER_PLIC_CORE5_IE_4__REG_ADDR (0x08002290)
#define TT_CLUSTER_PLIC_CORE6_IE_0__REG_OFFSET (0x00002300)
#define TT_CLUSTER_PLIC_CORE6_IE_0__REG_ADDR (0x08002300)
#define TT_CLUSTER_PLIC_CORE6_IE_1__REG_OFFSET (0x00002304)
#define TT_CLUSTER_PLIC_CORE6_IE_1__REG_ADDR (0x08002304)
#define TT_CLUSTER_PLIC_CORE6_IE_2__REG_OFFSET (0x00002308)
#define TT_CLUSTER_PLIC_CORE6_IE_2__REG_ADDR (0x08002308)
#define TT_CLUSTER_PLIC_CORE6_IE_3__REG_OFFSET (0x0000230C)
#define TT_CLUSTER_PLIC_CORE6_IE_3__REG_ADDR (0x0800230C)
#define TT_CLUSTER_PLIC_CORE6_IE_4__REG_OFFSET (0x00002310)
#define TT_CLUSTER_PLIC_CORE6_IE_4__REG_ADDR (0x08002310)
#define TT_CLUSTER_PLIC_CORE7_IE_0__REG_OFFSET (0x00002380)
#define TT_CLUSTER_PLIC_CORE7_IE_0__REG_ADDR (0x08002380)
#define TT_CLUSTER_PLIC_CORE7_IE_1__REG_OFFSET (0x00002384)
#define TT_CLUSTER_PLIC_CORE7_IE_1__REG_ADDR (0x08002384)
#define TT_CLUSTER_PLIC_CORE7_IE_2__REG_OFFSET (0x00002388)
#define TT_CLUSTER_PLIC_CORE7_IE_2__REG_ADDR (0x08002388)
#define TT_CLUSTER_PLIC_CORE7_IE_3__REG_OFFSET (0x0000238C)
#define TT_CLUSTER_PLIC_CORE7_IE_3__REG_ADDR (0x0800238C)
#define TT_CLUSTER_PLIC_CORE7_IE_4__REG_OFFSET (0x00002390)
#define TT_CLUSTER_PLIC_CORE7_IE_4__REG_ADDR (0x08002390)
#define TT_CLUSTER_PLIC_CORE0_THRESHOLD_REG_OFFSET (0x00200000)
#define TT_CLUSTER_PLIC_CORE0_THRESHOLD_REG_ADDR (0x08200000)
#define TT_CLUSTER_PLIC_CORE0_CLAIM_COMPLETE_REG_OFFSET (0x00200004)
#define TT_CLUSTER_PLIC_CORE0_CLAIM_COMPLETE_REG_ADDR (0x08200004)
#define TT_CLUSTER_PLIC_CORE1_THRESHOLD_REG_OFFSET (0x00201000)
#define TT_CLUSTER_PLIC_CORE1_THRESHOLD_REG_ADDR (0x08201000)
#define TT_CLUSTER_PLIC_CORE1_CLAIM_COMPLETE_REG_OFFSET (0x00201004)
#define TT_CLUSTER_PLIC_CORE1_CLAIM_COMPLETE_REG_ADDR (0x08201004)
#define TT_CLUSTER_PLIC_CORE2_THRESHOLD_REG_OFFSET (0x00202000)
#define TT_CLUSTER_PLIC_CORE2_THRESHOLD_REG_ADDR (0x08202000)
#define TT_CLUSTER_PLIC_CORE2_CLAIM_COMPLETE_REG_OFFSET (0x00202004)
#define TT_CLUSTER_PLIC_CORE2_CLAIM_COMPLETE_REG_ADDR (0x08202004)
#define TT_CLUSTER_PLIC_CORE3_THRESHOLD_REG_OFFSET (0x00203000)
#define TT_CLUSTER_PLIC_CORE3_THRESHOLD_REG_ADDR (0x08203000)
#define TT_CLUSTER_PLIC_CORE3_CLAIM_COMPLETE_REG_OFFSET (0x00203004)
#define TT_CLUSTER_PLIC_CORE3_CLAIM_COMPLETE_REG_ADDR (0x08203004)
#define TT_CLUSTER_PLIC_CORE4_THRESHOLD_REG_OFFSET (0x00204000)
#define TT_CLUSTER_PLIC_CORE4_THRESHOLD_REG_ADDR (0x08204000)
#define TT_CLUSTER_PLIC_CORE4_CLAIM_COMPLETE_REG_OFFSET (0x00204004)
#define TT_CLUSTER_PLIC_CORE4_CLAIM_COMPLETE_REG_ADDR (0x08204004)
#define TT_CLUSTER_PLIC_CORE5_THRESHOLD_REG_OFFSET (0x00205000)
#define TT_CLUSTER_PLIC_CORE5_THRESHOLD_REG_ADDR (0x08205000)
#define TT_CLUSTER_PLIC_CORE5_CLAIM_COMPLETE_REG_OFFSET (0x00205004)
#define TT_CLUSTER_PLIC_CORE5_CLAIM_COMPLETE_REG_ADDR (0x08205004)
#define TT_CLUSTER_PLIC_CORE6_THRESHOLD_REG_OFFSET (0x00206000)
#define TT_CLUSTER_PLIC_CORE6_THRESHOLD_REG_ADDR (0x08206000)
#define TT_CLUSTER_PLIC_CORE6_CLAIM_COMPLETE_REG_OFFSET (0x00206004)
#define TT_CLUSTER_PLIC_CORE6_CLAIM_COMPLETE_REG_ADDR (0x08206004)
#define TT_CLUSTER_PLIC_CORE7_THRESHOLD_REG_OFFSET (0x00207000)
#define TT_CLUSTER_PLIC_CORE7_THRESHOLD_REG_ADDR (0x08207000)
#define TT_CLUSTER_PLIC_CORE7_CLAIM_COMPLETE_REG_OFFSET (0x00207004)
#define TT_CLUSTER_PLIC_CORE7_CLAIM_COMPLETE_REG_ADDR (0x08207004)

#endif
